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INTEGRATED CIRCUITS
DATA SHEET
UDA1355H Stereo audio codec with SPDIF interface
Preliminary specification 2003 Apr 10
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 FEATURES General Control IEC 60958 input IEC 60958 output Digital I/O interface ADC digital sound processing DAC digital sound processing GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION IC control Microcontroller interface Clock systems IEC 60958 decoder IEC 60958 encoder Analog input Analog output Digital audio input and output Power-on reset APPLICATION MODES Static mode pin assignment Static mode basic applications Microcontroller mode pin assignment Microcontroller mode applications SPDIF SIGNAL FORMAT SPDIF channel encoding SPDIF hierarchical layers Timing characteristics L3-BUS DESCRIPTION Device addressing Register addressing Data write mode Data read mode 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 12 12.1 12.2 12.3 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 I2C-BUS DESCRIPTION Characteristics Bit transfer Byte transfer Data transfer Register address Device address Start and stop conditions Acknowledgment Write cycle Read cycle REGISTER MAPPING
UDA1355H
Address mapping Read/write registers mapping Read registers mapping LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
1 1.1 FEATURES General
UDA1355H
* 2.7 to 3.6 V power supply * Integrated digital interpolator filter and Digital-to-Analog Converter (DAC) * 24-bit data path in interpolator * No analog post filtering required for DAC * Integrated Analog-to-Digital Converter (ADC), Programmable Gain Amplifier (PGA) and digital decimator filter * 24-bit data path in decimator * Master or slave mode for digital audio data I/O interface * I2S-bus, MSB-justified, LSB-justified 16, 18, 20, and 24 bits formats supported on digital I/O interface. 1.2 Control * 32, 44.1 and 48 kHz output frequencies (including double and half of these frequencies) supported in microcontroller mode * Via microcontroller, 40 status bits can be set for left and right channel. 1.5 Digital I/O interface
* Supports sampling frequencies from 16 to 100 kHz * Supported static mode: - I2S-bus format - LSB-justified 16 and 24 bits format - MSB-justified format. * Supported microcontroller mode: - I2S-bus format - LSB-justified 16, 18, 20 or 24 bits format - MSB-justified format. * BCK and WS signals can be slave or master, depending on application mode. 1.6 ADC digital sound processing
* Controlled by means of static pins or microcontroller (L3-bus or I2C-bus) interface. 1.3 IEC 60958 input
* On-chip amplifier for converting IEC 60958 input to CMOS levels * Supports level I, II and III timing * Selectable IEC 60958 input channel, one of four * Supports input frequencies from 28 to 96 kHz * Lock indication signal available on pin LOCK * 40 status bits can be read for left and right channel via L3-bus or I2C-bus * Channel status bits available via L3-bus or I2C-bus: lock, pre-emphasis, audio sample frequency, two channel Pulse Code Modulation (PCM) indication and clock accuracy * Pre-emphasis information of incoming IEC 60958 bitstream available in register * Detection of digital data preamble, such as AC3, available on pin in microcontroller mode. 1.4 IEC 60958 output
* Supports sampling frequencies from 16 to 100 kHz * Analog front-end includes a 0 to +24 dB PGA in steps of 3 dB, selectable via microcontroller interface * Digital independent left and right volume control of +24 to -63.5 dB in steps of 0.5 dB via microcontroller interface * Bitstream ADC operating at 64fs * Comb filter decreases sample rate from 64fs to 8fs * Decimator filter (8fs to fs) made of a cascade of three FIR half-band filters. 1.7 DAC digital sound processing
* CMOS output level converted to IEC 60958 output signal * Full-swing digital signal, with level II timing using crystal oscillator clock * 32, 44.1 and 48 kHz output frequencies supported in static mode
* Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio sampling frequencies * Automatic de-emphasis when using IEC 60958 to DAC * Soft mute made of a cosine roll-off circuit selectable via pin MUTE or L3-bus interface 3
2003 Apr 10
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
* Programmable digital silence detector * Interpolating filter (fs to 64fs or fs to 128fs) comprising a recursive and a FIR filter in cascade * Selectable fifth-order noise shaper operating at 64fs or third-order noise shaper operating at 128fs (specially for low sampling frequencies, e.g. 16 kHz) generating bitstream for DAC * Filter Stream DAC (FSDAC) * In microcontroller mode: - Left and right volume control (for balance control) 0 to -78 dB and - - Left and right bass boost and treble control - Optional resonant bass boost control - Mixing possibility of two data streams. 2 GENERAL DESCRIPTION
UDA1355H
which can generate level II output signals with CMOS levels. In microcontroller mode the UDA1355H offers a large variety of possibilities for defining signal flows through the IC, offering a flexible analog, digital and SPDIF converter chip with possibilities for off-chip sound processing via the digital input and output interface. A lock indicator is available on pin LOCK when the IEC 60958 decoder and the clock regeneration mechanism is in lock. By default the DAC output and the digital data interface output are muted when the decoder is not in lock. The UDA1355H contains two clock systems which can run at independent frequencies, allowing to lock-on to an incoming SPDIF or digital audio signal, and in the mean time generating a stable signal by means of the crystal oscillator for driving, for example, the ADC or SPDIF output signal. Using the crystal oscillator (which requires a 12.288 MHz crystal) and the on-chip low jitter PLL, all standard audio sampling frequencies (fs = 32, 44.1 and 48 kHz including half and double these frequencies) can be generated.
The UDA1355H is a single-chip IEC 60958 decoder and encoder with integrated stereo digital-to-analog converters and analog-to-digital converters employing bitstream conversion techniques. The UDA1355H has a selectable one-of-four SPDIF input (accepting level I, II and III timing) and one SPDIF output 3 ORDERING INFORMATION TYPE NUMBER UDA1355H
PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
4 QUICK REFERENCE DATA SYMBOL Supplies VDDA1 VDDA2 VDDX VDDI VDDE IDDA1 DAC supply voltage ADC supply voltage crystal oscillator and PLL supply voltage digital core supply voltage digital pad supply voltage DAC supply current fs = 48 kHz; power-on fs = 96 kHz; power-on fs = 48 kHz; power-down fs = 96 kHz; power-down IDDA2 ADC supply current fs = 48 kHz; power-on fs = 96 kHz; power-on fs = 48 kHz; power-down fs = 96 kHz; power-down IDDX IDDI IDDE Tamb crystal oscillator and PLL supply current digital core supply current digital pad supply current ambient temperature fs = 48 kHz; power-on fs = 96 kHz; power-on fs = 48 kHz; all on fs = 96 kHz; all on fs = 48 kHz; all on fs = 96 kHz; all on Digital-to-analog converter; fi = 1 kHz; VDDA1 = 3.0 V Vo(rms) Vo (THD+N)/S output voltage (RMS value) output voltage unbalance total harmonic distortion-plus-noise to signal ratio IEC 60958 input; fs = 48 kHz at 0 dB at -20 dB at -60 dB; A-weighted IEC 60958 input; fs = 96 kHz at 0 dB at -60 dB; A-weighted S/N signal-to-noise ratio IEC 60958 input; code = 0; A-weighted fs = 48 kHz fs = 96 kHz cs channel separation - - - 98 96 100 - - -83 -37 - - - -88 -75 -37 - - 900 0.1 2.7 2.7 2.7 2.7 2.7 - - - - - - - - - - - - - - -40 3.0 3.0 3.0 3.0 3.0 4.7 4.7 1.7 1.7 10.2 10.4 0.2 0.2 0.9 1.2 18.2 34.7 0.5 0.7 - PARAMETER CONDITIONS MIN.
UDA1355H
TYP.
MAX.
UNIT
3.6 3.6 3.6 3.6 3.6 - - - - - - - - - - - - - - +85 - - - - - - -
V V V V V mA mA A A mA mA A A mA mA mA mA mA mA C
mV dB dB dB dB dB dB
- - -
dB dB dB
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL
PARAMETER
CONDITIONS Vo = -1.16 dBFS digital output fs = 48 kHz at 0 dB at -60 dB; A-weighted fs = 96 kHz at 0 dB at -60 dB; A-weighted
MIN. - - - - - - - - - - - -
TYP.
MAX. - - - - - - - - -
UNIT
Analog-to-digital converter; fi = 1 kHz; VDDA2 = 3.0 V Vi(rms) Vi (THD+N)/S input voltage (RMS value) input voltage unbalance total harmonic distortion-plus-noise to signal ratio 1.0 0.1 -85 -35 -85 -35 97 95 100 V dB dB dB dB dB dB dB dB
S/N
signal-to-noise ratio
code = 0; A-weighted fs = 48 kHz fs = 96 kHz
cs External crystal fxtal CL(xtal) Device reset trst Ptot
channel separation
crystal frequency crystal load capacitor
12.288 - 10 - -
MHz pF s
reset time
250
Power consumption total power consumption IEC 60958 input; fs = 48 kHz DAC in playback mode DAC in Power-down mode - - 74 63 - - mW mW
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2003 Apr 10
XTALIN XTALOUT VINL VINR RESET RTCB WSI DATAI BCKI SPDIF0
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Philips Semiconductors
Stereo audio codec with SPDIF interface
BLOCK DIAGRAM
VDDX 12 13 14 34
VSSX 15
VADCP VDDA2 CLK_OUT 32 37 11 CLOCK AND TIMING
VDDI 27
VREF 38
VDDE 6
VDDA1 39
XTAL
ADC COMB FILTER ADC DECIMATOR
36
AUDIO FEATURE PROCESSOR
AUDIO FEATURE PROCESSOR
DAC INTERPOLATOR NOISE SHAPER DAC
40
VOUTL
42
VOUTR
16 43 2 3 1 23 24 25 26 SLICER IEC 60958 DECODER IEC 60958 ENCODER DATA IN INPUT AND OUTPUT SELECT
44
MUTE
9 DATA OUT 8 10
WSO DATAO BCKO
7
SPDIF1 SPDIF2 SPDIF3
5
SPDIFOUT
SLICER_SEL0 SLICER_SEL1 LOCK
21 22 4
CONTROL INTERFACE
UDA1355H
Preliminary specification
33 VADCN
35
28 VSSIS
29
30
31
20
17 18 19 MODE0 MODE2
7 VSSE
41
MGU826
UDA1355H
MP0 MP1
MP2 SEL_STATIC
VSSA1
VSSA2
MODE1
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
6 PINNING SYMBOL BCKI WSI DATAI LOCK SPDIFOUT VDDE VSSE DATAO WSO BCKO CLK_OUT VDDX XTALIN XTALOUT VSSX RESET MODE0 MODE1 MODE2 SEL_STATIC SLICER_SEL0 SLICER_SEL1 SPDIF0 SPDIF1 SPDIF2 SPDIF3 VDDI VSSIS MP0 MP1 MP2 VADCP VADCN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 PAD(1) bpt4mtht5v bpt4mtht5v iptht5v op4mc op4mc vdde vsse ops5c bpt4mtht5v bpt4mtht5v op4mc vddco apio apio vssco ipthdt5v apio bpts5tht5v bpts5tht5v apio bpts5tht5v bpts5tht5v apio apio apio apio vddi vssis apio iptht5v iic400kt5v vddco vssco DESCRIPTION bit clock input (master or slave) word select input (master or slave) digital data input PLL lock indicator output SPDIF output digital pad supply voltage digital pad ground digital data output word select output (master or slave) bit clock output (master or slave) clock output; 256fs or 384fs crystal oscillator and PLL supply voltage crystal oscillator input crystal oscillator output crystal oscillator and PLL ground reset input
UDA1355H
mode selection input 0 for static mode or microcontroller mode (grounded for I2C-bus) mode selection input 1 for static mode or AO address input and output for microcontroller mode mode selection input 2 for static mode or U_RDY output for microcontroller mode selection input for static mode, I2C-bus mode or L3-bus mode SPDIF slicer selection input 0 for static mode and USER bit output for microcontroller mode SPDIF slicer selection input 1 for static mode and AC3 preamble detect output for microcontroller mode SPDIF input 0 SPDIF input 1 SPDIF input 2 SPDIF input 3 digital core supply voltage digital core ground multi-purpose pin 0: frequency select for static mode, not used for microcontroller mode multi-purpose pin 1: SFOR1 for static mode, SCL for I2C-bus mode and L3CLOCK for L3-bus mode multi-purpose pin 2: SFOR0 for static mode, SDA for I2C-bus mode and L3DATA for L3-bus mode positive ADC reference voltage negative ADC reference voltage
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL VINL VSSA2 VINR VDDA2 VREF VDDA1 VOUTL VSSA1 VOUTR RTCB MUTE Note 1. See Table 1. Table 1
PIN 34 35 36 37 38 39 40 41 42 43 44
PAD(1) apio vssco apio vddco apio vddco apio vssco apio ipthdt5v iipthdt5v ADC left channel input ADC ground ADC right channel input ADC supply voltage
DESCRIPTION
reference voltage for ADC and DAC DAC supply voltage DAC left channel output DAC ground DAC right channel output test control input DAC mute input
Pad description DESCRIPTION input pad; push-pull; TTL with hysteresis; 5 V tolerant input pad; push-pull; TTL with hysteresis; pull-down; 5 V tolerant output pad; push-pull; 4 mA output drive; CMOS output pad; push-pull; 5 ns slew rate control; CMOS bidirectional pad; push-pull input; 3-state output; 4 mA output drive; TTL with hysteresis; 5 V tolerant bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL with hysteresis; 5 V tolerant I2C-bus pad; 400 kHz I2C-bus specification with open drain; 5 V tolerant analog pad; analog input or output analog supply pad analog ground pad digital supply pad digital ground pad digital core supply pad digital core ground pad
PAD iptht5v ipthdt5v op4mc ops5c bpt4mtht5v bpts5tht5v iic400kt5v apio vddco vssco vdde vsse vddi vssis
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
42 VOUTR
39 VDDA1
41 VSSA1
35 VSSA2
44 MUTE
38 VREF
43 RTCB
handbook, full pagewidth
37 VDDA2
40 VOUTL
36 VINR
34 VINL
BCKI 1 WSI 2 DATAI 3 LOCK 4 SPDIFOUT 5 VDDE 6 VSSE 7 DATAO 8 WSO 9 BCKO 10 CLK_OUT 11
33 VADCN 32 VADCP 31 MP2 30 MP1 29 MP0
UDA1355H
28 VSSIS 27 VDDI 26 SPDIF3 25 SPDIF2 24 SPDIF1 23 SPDIF0
SLICER_SEL0 21
SLICER_SEL1 22
VDDX 12
XTALIN 13
XTALOUT 14
VSSX 15
RESET 16
MODE0 17
MODE1 18
MODE2 19
SEL_STATIC 20
MGU828
Fig.2 Pin configuration.
7 7.1
FUNCTIONAL DESCRIPTION IC control
Table 2
Control mode selection via pin SEL_STATIC LEVEL HIGH MID LOW MODE static mode I2C-bus mode L3-bus mode
The UDA1355H can be controlled either via static pins or via the microcontroller serial hardware interface being the I2C-bus with a clock up to 400 kHz or the L3-bus with a clock up to 2 MHz. It is recommended to use the microcontroller interface since this gives full access to all the IC features. The two microcontroller interfaces only differ in interface format. The register addresses and features that can be controlled are identical for L3-bus mode and I2C-bus mode. The UDA1355H can operate in three control modes: * Static mode with limited features * L3-bus mode with full featuring * I2C-bus mode with full featuring. The modes are selected via the 3-level pin SEL_STATIC according to Table 2. 2003 Apr 10 10
7.2
Microcontroller interface
The UDA1355H has a microcontroller interface and all the sound processing features and system settings can be controlled by the microcontroller. The controllable settings are: * Restoring L3-bus defaults * Power-on settings for all blocks * Digital interface input and output formats * Volume settings for the decimator * PGA gain settings
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
* Set two times 40 bits of channel status bits of the SPDIF output * Select one of four SPDIF input sources * Enable digital mixer inside interpolator * Control mute and mixer volumes of digital mixer * Selection of filter mode and settings of treble and bass boost for the interpolator (DAC) section * Volume settings of interpolator * Selection of soft mute via cosine roll-off (only effective in L3-bus control mode) and bypass of auto mute * Selection of de-emphasis * Enable and control of digital mixer inside interpolator. The readable settings are: * Mute status of interpolator * PLL lock and adaptive lock * Two times 40 bits of channels status bits of the SPDIF input signal. 7.3 Clock systems 48 kHz 44.1 kHz 32 kHz Table 3 Output frequencies
UDA1355H
OUTPUT FREQUENCY BASIC AUDIO FREQUENCY MICROCONTROLLER MODE 256 x 16 kHz 384 x 16 kHz 256 x 32 kHz 384 x 32 kHz 256 x 64 kHz 384 x 64 kHz 256 x 22.05 kHz 384 x 22.05 kHz 256 x 44.1 kHz 384 x 44.1 kHz 256 x 88.2 kHz 384 x 88.2 kHz 256 x 24 kHz 384 x 24 kHz 256 x 48 kHz 384 x 48 kHz 256 x 96 kHz 384 x 96 kHz Remarks: * If an application mode is selected which does not need a crystal oscillator, the crystal oscillator cannot be omitted. The reason is that the interpolator switches to the crystal clock when an SPDIF input signal is removed. This switch prevents the noise shaper noise from moving inside the audio band as the PLL gradually decreases in frequency. * If no accurate output frequency is needed, the crystal can be replaced with a resonator. * Instead of the crystal, a 12.288 MHz system clock can be applied to pin XTALIN. The block diagram of the crystal oscillator and the PLL circuit is given in Fig.3. 256 x 48 kHz 256 x 44.1 kHz 256 x 32 kHz STATIC MODE
The UDA1355H has two clock systems. The first system uses an external crystal of 12.288 MHz to generate the audio related system clocks. Only a crystal with a frequency of 12.288 MHz is allowed. The second system is a PLL which locks on the SPDIF or incoming digital audio signal (e.g. I2S-bus) and recovers the system clock. 7.3.1 CRYSTAL OSCILLATOR CLOCK SYSTEM
The crystal oscillator and the on-chip PLL and divider circuit can be used to generate internal and external clock signals related to standard audio sampling frequencies (such as 32, 44.1 and 48 kHz including half and double of these frequencies). The audio frequencies supported in either microcontroller mode or static mode are given in Table 3.
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
7.3.4
12.288 handbook, halfpage MHz 13 14 XTALOUT 256fs or 384fs clock CLK_OUT 11 PLL clock CRYSTAL OSCILLATOR PLL MODULE
UDA1355H
CLOCK OUTPUT
XTALIN
The UDA1355H has a clock output pin (pin CLK_OUT), which can be used to drive other audio devices in the system. In microcontroller mode the output clock is 256fs or 384fs. In static mode the output clock is 256 times 32, 44.1 and 48 kHz. The source of the output clock is either the crystal oscillator or the PLL, depending on the selected application and control mode. 7.4 IEC 60958 decoder
L3-bus or I2C-bus register setting
UDA1355H
MGU830
Fig.3 Crystal oscillator clock system.
The UDA1355H IEC 60958 decoder can select one of four SPDIF input channels. An on-chip amplifier with hysteresis amplifies the SPDIF input signal to CMOS level, making it possible to accept both analog and digital SPDIF signals (see Fig.5).
7.3.2
PLL CLOCK SYSTEM
handbook, halfpage
The PLL locks on the incoming digital data of the SPDIF or WS input signal. The PLL recovers the clock from the SPDIF or WSI signal and removes jitter to produce a stable system clock (see Fig.4).
10 nF
75
180 pF
SPDIF0 SPDIF1 SPDIF2 SPDIF3
23 24 25 26
select SPDIF source
UDA1355H UDA1355H
MGU829
SPDIF0 SPDIF1 SPDIF2 SPDIF3
23 24 25 26 SLICER IEC 60958 DECODER
Fig.5 IEC 60958 input circuit.
7.4.1
PLL 256fs or 384fs
MGU827
AUDIO DATA
WSI
2
From the incoming SPDIF bitstream 24 bits of data for the left and right channel are extracted. There is a hard mute (not a cosine roll-off mute) if the IEC 60958 decoder is out of lock or detects bi-mark phase encoding violations. The lock indicator and the key channel status bits are accessible in L3-bus mode. The UDA1355H supports the following sample frequencies and data rates, including half and double of these frequencies: * fs = 32 kHz; resulting in a data rate of 2.048 Mbit/s * fs = 44.1 kHz; resulting in a data rate of 2.8224 Mbit/s * fs = 48 kHz; resulting in a data rate of 3.072 Mbit/s.
Fig.4 PLL clock system.
7.3.3
WORD SELECTION DETECTION CIRCUIT
This circuit is clocked by the 12.288 MHz crystal oscillator clock and generates a Word Selection (WS) detection signal. If the WS detector does not detect any WS edge, defined as 7 times LOW and 7 times HIGH, then the WS detection signal is LOW. This information can be used to set the clock for the noise shaper in the interpolator. This will prevent noise shaper noise in the audio band.
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
7.4.2 CHANNEL STATUS AND USER BITS 7.5 IEC 60958 encoder
UDA1355H
As well as the data bits there are several IEC 60958 key channel status bits: * Pre-emphasis and audio sampling frequency bits * Two channel PCM indicator bits * Clock accuracy bits. In total 40 status bits per channel are recovered from the incoming IEC 60958 bitstream. These are readable via the microcontroller interface. User bits, which can contain a large variety of data, such as CD text, are output to pin SLICER_SEL0 (see Table 4). In microcontroller mode this signal contains the raw user bits extracted from the SPDIF bitstream. Signal U_RDY gives a pulse on pin MODE2 each time there is a new user bit available. Both signals can be used by an external microcontroller to grab and decode the user bits. Table 4 Signal names in microcontroller mode PIN NAME SLICER_SEL0 MODE2 SLICER_SEL1 7.4.3 DIGITAL DATA SIGNAL NAME USER U_RDY AC3
When using the crystal oscillator clock, the IEC 60958 encoder output is a full-swing digital signal with level II timing. When the recovered clock from the PLL is used the IEC 60958 encoder will function correctly but will not meet level II timing requirements. 7.5.1 STATIC MODE
All user and channel status bits are set to logic 0. This is default value specified by IEC. In static mode 0 and 2, the selected SPDIF input channel can be looped through to pin SPDIFOUT (see Fig.6). 7.5.2 MICROCONTROLLER MODE
Two times 40 channel status bits can be set. Default value for each status bit is logic 0. When setting the channel status bits, it is possible to set only the left channel status bits and have the bits copied to the right channel. The procedure of writing the channel status bits is as follows: 1. Set bit SPDO_VALID = 0 to prevent immediately sending the status bits during writing. 2. Set bit l_r_copy = 1 if the right channel needs the same status bits as the left channel or set bit l_r_copy = 0 if the right channel needs different status bits to the left channel. 3. Write the left and right channel status bits. 4. Set bit SPDO_VALID = 1 after writing all channel status bits to the register. Starting from the next SPDIF block the IEC 60958 encoder will use the new status bits. In microcontroller modes 2 and 13, the selected SPDIF input channel can be looped through to pin SPDIFOUT (see Fig.6).
Audio and digital data can be transmitted in the SPDIF bitstream. The PCM channel status bit should be set to logic 1 if the SPDIF bitstream is carrying digital data instead of audio data, but in practice it proves that not all equipment handles these channel status bits properly. In the UDA1355H, digital data is detected via bit PCM, or via the sync bytes as specified by IEC. These sync bytes are two sync words, F872H and 4E1FH (two subframes) preceded by four or more subframes filled with zeros. Signal AC3 is kept HIGH for 4096 frames when the UDA1355H detects this burst preamble. Signal AC3 is present on pin SLICER_SEL1 in microcontroller mode (see Table 4).
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
handbook, full pagewidth
SPDOUT_SEL1 SPDOUT_SEL0 SPDIF0 SPDIF1 SPDIF2 SPDIF3 23 24 25 26 SLICER select SPDIF source SPDIF source 21, 22 SLICER_SEL [1:0]
UDA1355H
SPDOUT_SEL2 IEC 60958 DECODER MODE [3:0]
5
SPDIF OUT
IEC 60958 ENCODER 17 to 19 20
MGU833
MODE [2:0] SEL_STATIC
Fig.6 Selection options for SPDIF output.
7.6 7.6.1
Analog input ADC
7.6.2
DECIMATION
The analog input is equipped with a Programmable Gain Amplifier (PGA) which can be controlled via the microcontroller interface. The control range is from 0 to 24 dB gain in 3 dB steps independent for the left and right channels. In applications in with a 2 V (RMS) input signal, a 12 k resistor must be used in series with the input of the ADC. The 12 k resistor forms a voltage divider together with the internal ADC resistor and ensures that the voltage, applied to the input of the IC, never exceeds 1 V (RMS). In the application for a 2 V (RMS) input signal, the PGA must be set to 0 dB. When a 1 V (RMS) input signal is applied to the ADC in the same application, the PGA gain must be set to 6 dB. An overview of the maximum input voltages allowed with and without an external resistor and the PGA gain setting is given in Table 5. Table 5 Maximum input voltage; VDD = 3 V PGA GAIN SETTING 0 dB 6 dB Absent 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS)
The decimation from 64fs is performed in two stages: comb filter and decimation filter. The first stage realizes a sin x fourth-order ----------- characteristic with a decimation factor x of eight. The second stage consists of three half-band filters each decimating by a factor of two. Table 6 shows the characteristics. Table 6 Decimation filter characteristics ITEM Pass-band ripple Stop band Dynamic range Overall gain from ADC input to digital output Note 1. The output is not 0 dB when VI(rms) = 1 V at VDD = 3 V. This is because the analog components can spread over the process. When there is no external resistor, the -1.16 dB scaling prevents clipping caused by process mismatch. In the ADC path there are left and right independent digital volume controls with a range from +24 to -63.5 dB and - dB. This volume control is also used as a digital linear mute that can be used to prevent plops when powering-up or powering down the ADC front path. CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.45fs DC; VI = 0 dB; note 1 VALUE (dB) 0.02 -60 140 -1.16
EXTERNAL RESISTOR (12 k) Present
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
7.6.3 DC FILTERING
UDA1355H
In the decimator there are two digital DC blocking circuits. The first blocking circuit is in front of the volume control to remove DC bias from the ADC output. The DC bias is added in the ADC to prevent audio band Idle tones occurring in the noise shaper. With the DC components removed, a signal gain of 24 dB can be achieved. The second blocking circuit removes the DC components introduced by the decimator stage. 7.6.4 OVERLOAD DETECTION
* Support for 1fs and 2fs input data rate and 192 kHz audio via I2S-bus. The stereo interpolator has the following sound features: * Linear volume control using 14-bit coefficients with 0.25 dB steps: range 0 to -78 dB and - dB; hold for master volume and mixing volume control * A cosine roll-off soft mute with 32 coefficients; each coefficient is used for four samples, in total 128 samples are needed to fully mute or de-mute (approximately 3 ms at fs = 44.1 kHz) * Independent selectable de-emphasis for 32, 44.1, 48 and 96 kHz for both channels * Treble is the selectable positive gain for high frequencies. The edge frequency of the treble is fixed and depends on the sampling frequency. Treble can be set independently for left and right channel with two settings: - fc = 1.5 kHz; fs = 44.1 kHz; 0 to 6 dB gain range with 2 dB steps - fc = 3 kHz; fs = 44.1 kHz; 0 to 6 dB gain range with 2 dB steps. * Normal bass boost is the selectable positive gain for low frequencies. The edge frequency of the bass boost is fixed and depends on the sampling frequency. Normal bass boost can be set independently for the left and right channel with two sets: - fc = 250 Hz; fs = 44.1 kHz; 0 to 18 dB gain range with 2 dB steps - fc = 300 Hz; fs = 44.1 kHz; 0 to 24 dB gain range with 2 dB steps. * Resonant bass boost optional function is selected if bit BASS_SEL = 1. When selected, the characteristics are determined by six 14-bit coefficients. Resonant bass boost controls the left and right channel with the same characteristics. When resonant bass boost is selected, the treble control also changes to a single control for both channels following the gain setting of the left channel. A software program is available for users to generate the required six 14-bit coefficients by entering the desired centre frequency (fc), positive or negative peak gain, sampling frequency (fs) and shape factor (see Figs 7 and 8).
Bit OVERFLOW = 1 when the output data in the left or right channel is larger than -1.16 dB of the maximum possible digital swing. This condition is set for at least 512fs cycles (that is 11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. 7.7 7.7.1 Analog output AUDIO FEATURE PROCESSOR
The audio feature processor provides automatic de-emphasis for the IEC 60958 bitstream. In microcontroller mode all features are available and there is a default mute on start up. 7.7.2 INTERPOLATING FILTER
The digital filter interpolates from 1fs to 64fs, or from 1fs to 128fs, by cascading a half-band filter and a FIR filter. The stereo interpolator has the following basic features: * 24-bit data path * Mixing of two channels: - To prevent clipping inside the core, there is an automatic signal level correction of -6 dB scaling before mixing and +6 dB gain after digital volume control - Position of mixing can be set before or after bass boost and treble - Master volume control and mute with independent left and right channel settings for balance control - Independently left and right channel de-emphasis, volume control and mute (no left or right) - Output of the mixer is to the I2S-bus or IEC 60958 decoder. * Full FIR filter implementation for all the upsampling filters * Integrated digital silence detection for left and right channels with selectable silence detection time 2003 Apr 10 15
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 7 Interpolation filter characteristics CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.4535fs VALUE (dB) 0.035 -60 140
UDA1355H
ITEM Pass-band ripple Stop band Dynamic range 7.7.3
mute controls available: for source 1, for source 2 and for the master (sum) signal. All three volume ranges can be controlled in 0.25 dB steps. To prevent clipping inside the mixer, the signals are scaled with -6 dB before mixing, therefore the sum of the two signals is always equal to or lower than 0 dB. After the mixing there is a 6 dB gain in the master volume control. This means that at the analog output the signal can clip, but the clipping can be undone by decreasing the master volume control. The output of the mixer is available via the I2S-bus output or via the SPDIF output. The output signal of the mixer is scaled to a maximum of 0 dB, so the digital output can never clip.
DIGITAL MIXER
The UDA1355H has a digital mixer inside the interpolator. The digital mixer can be used as a cross over or a selector. A functional block diagram of the mixer mode is shown in Fig.9. This mixer can be used in microcontroller mode only. The UDA1355H can be set to the mixer mode by setting bit MIX = 1. In the mixer mode, there are three volume and
handbook, halfpage
10
MGU832
handbook, halfpage
10
MGU831
gain 8 (dB) 6 4 2 0 -2 -4 -6 -8 -10 1 10 102 103
gain 8 (dB) 6 4 2 0 -2 -4 -6 -8 -10 1 10 102 103
f (Hz))
f (Hz))
fc = 70 Hz fs = 44.1 kHz
Peak gain = 10 dB Shape factor = 1.4142
fc = 70 Hz fs = 44.1 kHz
Peak gain = 10 dB Shape factor = 1.4142
Fig.7 Resonant bass boost example 1.
Fig.8 Resonant bass boost example 2.
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
handbook, full pagewidth
channel 2 DE-EMPHASIS VOLUME AND MUTE
mixing before sound features
mixing after sound features 1fs
UDA1355H
L3/I2C bit VOLUME AND MUTE BASS-BOOST AND TREBLE MASTER VOLUME AND MUTE to interpolation filter and DAC output
DE-EMPHASIS channel 1
INT. FILTER
2fs
output of mixer
MGU834
Fig.9 Digital mixer (DAC) inside the interpolator DSP.
7.7.4
DIGITAL SILENCE DETECTOR
7.7.6
FILTER STREAM DAC
The UDA1355H is equipped with a digital silence detector. This detects whether a certain amount of consecutive samples are 0. The number of samples can be set with bits SD_VALUE[1:0] to 3200, 4800, 9600 or 19600 samples. The digital silence detection status can be read via the microcontroller interface. 7.7.5 NOISE SHAPER (DAC)
The noise shaper shifts in-band quantization noise to frequencies above the audio band. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). This noise shaping technique enables high signal-to-noise ratios to be achieved. The UDA1355H is equipped with two noise shapers: * A third-order noise shaper operating at 128fs. Which is used at low sampling frequencies (8 to 16 kHz) to prevent noise shaper noise shifting into the audio band for the fifth-order noise shaper * A fifth-order noise shaper operating at 64fs. Which is used at high sampling frequencies (from 32 kHz upwards). When the noise shaper changes, the clock to the FSDAC changes and the filter characteristic of the FSDAC also changes. The effect on the roll of is compensated by selecting the filter matching speed and order of the noise shaper.
The FSDAC is a semi digital reconstruction filter that converts the 1-bit data bitstream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the operational amplifier output. In this way, very high signal-to-noise performance and low clock jitter sensitivity are achieved. A post filter is not needed due to the inherent filter function of the FSDAC. On-chip amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the supply voltage. 7.7.7 DAC MUTE
The DAC and interpolator can be muted by setting pin MUTE to a HIGH level. The output signal is muted to zero via a cosine roll-off curve and the DAC is powered down. When pin MUTE is at LOW level the signal rise follows the same cosine curve. To prevent plops in case of changing inputs, clock to the DAC or application modes, a special mute circuit for the DAC is implemented (see Table 8). In all application modes in which the DAC is active the DAC can be muted by pin MUTE. The microcontroller mute bits and pin MUTE act as an OR function.
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 8 Muting to prevent plopping BIT OCCASION MT1 Input selection Select channel 1 source Select channel 2 source Select chip mode PLL is source for the DAC Crystal is source for the DAC - - - - - - - - - - - - - - - - - - - - x x x - - x - - MT2 MTM
UDA1355H
DE-MUTE CONDITION
no mute after selection no mute after selection
wait until PLL is locked again no mute after selection
Select between microcontroller mode and static mode PLL is source for the DAC Crystal is source for the DAC Audio features Select noise shaper order Select FSDAC output polarity Select SPDIF input Select mixer Select mixer position Select crystal clock source 7.8 Digital audio input and output x x x - - x no mute after selection no mute after selection PLL is locked again no mute needed no mute needed no mute after selection x x wait until PLL is locked again no mute after selection
* LSB-justified; 18 bits * LSB-justified; 20 bits * LSB-justified; 24 bits * MSB-justified. 7.9 Power-on reset
The selection of the digital audio input and output formats and master or slave modes differ for static and microcontroller mode. In master mode, when 256fs output clock is selected and the digital interface is master, the BCK output clock will be 64fs. In case 384fs output clock is selected, the BCK output clock will be 48fs. In the static mode the digital audio input formats are: * I2S-bus * LSB-justified; 16 bits * LSB-justified; 24 bits * MSB-justified. The digital audio output formats are: * I2S-bus * MSB-justified. In the microcontroller mode, the following formats are independently selectable: * I2S-bus * LSB-justified; 16 bits
The UDA1355H has a dedicated reset pin with an internal pull-down resistor. In this way a Power-on reset circuit can be made with a capacitor and a resistor at pin RESET. The external resistor is needed since the pad is 5 V tolerant. This means that there is a transmission gate in series with the input and the resistor inside the pad cannot be seen from the outside world (see Fig.10). The reset timing is determined by the external pull-down resistor and the external capacitor which is connected to pin RESET. At Power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the microcontroller mode. Since the bit controlling the clock of the synchronous registers is set to enable, the synchronous registers are also reset.
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
8
handbook, halfpage
UDA1355H
APPLICATION MODES
Transmission gate for 5V tolerance
In this chapter the application modes for static mode and microcontroller mode are described. The UDA1355H can be controlled by static pins, the L3-bus or I2C-bus interface. Due to the limitations imposed by the pin count, only basic functions are available in static mode. For optimum use of the UDA1355H features, the microcontroller mode is strongly recommended.
RESET
16
UDA1355H
VSS
MGU835
Fig.10 5 V tolerant pull-down input pad.
The clock should be running during the reset time. When no clock can be guaranteed in microcontroller mode, a soft reset should be given when the system is running by writing to register 7FH.
There are 11 application modes available in the static mode and 14 application modes in microcontroller mode. The application modes are explained in the two sections: Section 8.2 explains the application modes 0 to 10. Section 8.4 explains the more advanced features of modes 0 to 10 and modes 12 to 14 available in the microcontroller mode. 8.1 Static mode pin assignment
The default values for all non-pin controlled settings are identical to the start-up defaults from the microcontroller mode. Whether BCK and WS are master or slave depends on the selected application mode. Table 9 defines the pin functions in static mode.
Table 9 PIN 4
Static mode pin assignment STATIC MODE SYMBOL LOCK LEVEL LOW HIGH DESCRIPTION IEC 60958 decoder out of lock (when SPDIF input) or clock regeneration out of lock (I2S-bus input) IEC 60958 decoder in lock (when SPDIF input) or clock regeneration in lock (I2S-bus input) normal operation reset select application mode; see Table 10 static pin control microcontroller mode IEC 60958 input from pin SPDIF0 IEC 60958 input from pin SPDIF1 IEC 60958 input from pin SPDIF2 IEC 60958 input from pin SPDIF3 select 44.1 kHz sampling frequency for the crystal oscillator, note 1 select 32 kHz sampling frequency for the crystal oscillator, note 1 select 48 kHz sampling frequency for the crystal oscillator, note 1
16 17, 18, 19 20 22, 21
RESET MODE0, MODE1, MODE2 SEL_STATIC SLICER_SEL1, SLICER_SEL0
LOW HIGH - HIGH LOW LOW, LOW LOW, HIGH HIGH, LOW HIGH, HIGH
29
FREQ_SEL
LOW MID HIGH
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
PIN 30, 31
STATIC MODE SYMBOL SFOR1, SFOR0
LEVEL LOW, LOW LOW, HIGH HIGH, LOW HIGH, HIGH
DESCRIPTION set I2S-bus format for digital data input and output interface set LSB-justified 16 bits format for digital data input interface and MSB-justified format for digital data output interface set LSB-justified 24 bits format for digital data input interface and MSB-justified format for digital data output interface set MSB-justified format for digital data input and output interface normal operation mute active
44
MUTE
LOW HIGH
Note 1. FPLL 256fs is output from pin CLKOUT in PLL locked static mode. 8.2 Static mode basic applications
The static application modes are selected with the pins MODE2, MODE1 and MODE0, with pin MODE0 being a 3-level pin. In Table 10, the encoding of the pins MODE[2:0] is given. Table 10 Static mode basic applications MODE SELECTION PINS(1) MODE MODE2 0 1 2 3 4 5 6 7 8 9 10 11 Notes 1. In column mode selection pins means: L: pin at 0 V; M: pin at half VDDD; H: pin at VDDD. 2. In column clock means: xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL. L L L L L L H H H H H H MODE1 L L L H H H L L L H H H MODE0 L M H L M H L M H L M H SPDIF INPUT PLL - PLL - - - - PLL - PLL PLL SPDIF OUTPUT PLL PLL PLL xtal xtal xtal PLL xtal xtal xtal xtal CLOCK(2) I2S-BUS ADC - - - xtal xtal xtal xtal xtal xtal - - DAC PLL PLL PLL - xtal xtal PLL PLL PLL xtal PLL not used INPUT SLAVE - PLL PLL - xtal xtal PLL - PLL xtal xtal I2S-BUS OUTPUT MASTER PLL - PLL xtal xtal xtal xtal xtal xtal PLL PLL PLL LOCKS ON INPUT SPDIF I2S-bus SPDIF - - - I2S-bus SPDIF I2S-bus SPDIF SPDIF
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
The first 11 application modes are given in this section. Schematic diagrams of these application modes are given in Table 11. In this table the basic features are mentioned and also the extra features in case of microcontroller mode are given. It should be noted that the blocks running at the crystal clock (XTAL) are marked unshaded while the blocks running at the PLL clock are shaded. Table 11 Overview of static mode basic applications MODE 0 Data path: * Input SPDIF to outputs DAC, I2S or SPDIFOUT via loop through. Features: * System locks onto the SPDIF input signal * BCK and WS are master * Microcontroller mode: - DAC sound features can be used - SPDIF input channel status bits (two times 40 bits) can be read.
SPDIF IN I2S OUTPUT
MGU836
FEATURES
SCHEMATIC
PLL
SPDIF LOCK
MUTE DAC SPDIFOUT
I 2S master
1
Data path: * Input I2S to outputs DAC or SPDIF (level II not guaranteed: depends on I2S-bus clock). Features: * System locks onto the WSI signal * BCKI and WSI are slave * Microcontroller mode: - DAC sound features can be used - SPDIF output channel status bits (two times 40 bits) setting.
I 2S slave I2S INPUT
MGU837
PLL
I 2S LOCK
MUTE DAC
SPDIF OUT
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE 2 Data path:
FEATURES * Input SPDIF to outputs I2S or SPDIFOUT via loop through * Input I2S to output DAC. Features: * Possibility to process input SPDIF via I2S-bus using an external DSP and then to output DAC * System locks onto the SPDIF input signal * I2S input and output with BCK and WS are master * Microcontroller mode: see Section 8.4.
SCHEMATIC
PLL
SPDIF LOCK
MUTE DAC SPDIFOUT
SPDIF IN I2S INPUT I 2S slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715)
MGU838
I 2S OUTPUT I 2S master
3
Data path: * Input ADC to outputs I2S or SPDIF. Features: * Crystal oscillator generates the clocks * Microcontroller mode: - PGA gain setting - Volume control in decimator setting - SPDIF output channel status bits (two times 40 bits) setting.
SPDIF OUT I 2S OUTPUT
MGU839
XTAL ADC
I 2S master
4
Data path: * Input ADC to output I2S * Input I2S to outputs DAC or SPDIF. Features: * Possibility to process input ADC via I2S-bus using a external DSP and then to outputs DAC or SPDIF * Crystal oscillator generates the clocks * I2S input and output with BCK and WS are master * Microcontroller mode: see Section 8.4.
ADC DAC SPDIF OUT I 2S INPUT I 2S slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715)
MGU840
XTAL MUTE
I 2S OUTPUT I 2S master
2003 Apr 10
22
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE 5 Data path:
FEATURES * Input ADC to outputs I2S or SPDIF * Input I2S to output DAC. Features: * Possibility to process input ADC via I2S-bus using an external DSP and then to output DAC * Crystal oscillator generates the clocks * I2S input and output with BCK and WS are master * Microcontroller mode: see Section 8.4.
ADC XTAL
SCHEMATIC
MUTE DAC SPDIF OUT I2S INPUT I 2S slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715)
MGU841
I 2S OUTPUT I 2S master
6
Data path: * Input ADC to output I2S * Input I2S to outputs DAC or SPDIF (level II not guaranteed: depends on I2S-bus clock). Features: * Possibility to process input ADC via I2S-bus using an external DSP and then to outputs DAC or SPDIF * Crystal oscillator generates the clocks for input ADC and output I2S * WSI is slave * WSO is master * Microcontroller mode: see Section 8.4.
EXTERNAL DSP (SAA7715)
MGU842
XTAL ADC
PLL
I 2S LOCK
MUTE DAC
SPDIF OUT I2S INPUT I 2S slave I 2S OUTPUT I 2S master
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE 7 Data path:
FEATURES * Input SPDIF to output DAC * Input ADC to outputs SPDIF or I2S. Features: * Crystal oscillator generates the clocks for outputs SPDIF and I2S * PLL locks onto the SPDIF input signal * WS of I2S output is master * Microcontroller mode: - Decimator features can be used - DAC sound features can be used - SPDIF input channel status bits (two times 40 bits) can be read - SPDIF output channel status bits (two times 40 bits) setting.
SPDIF IN XTAL ADC
SCHEMATIC
PLL
SPDIF LOCK
MUTE DAC SPDIF OUT I 2S OUTPUT
MGU843
I 2S master
8
Data path: * Input ADC to outputs SPDIF or I2S * Input I2S to output DAC. Features: * Possibility to process input ADC, via I2S-bus using an external DSP and then to output DAC * Crystal oscillator generates the clocks for outputs SPDIF and I2S * WSI is slave * WSO master * Microcontroller mode: - Decimator features can be used - DAC sound features can be used - SPDIF output channel status bits (two times 40 bits) setting.
I2S INPUT I 2S slave EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715)
MGU844
XTAL ADC
PLL
I 2S LOCK
MUTE DAC SPDIF OUT I 2S OUTPUT I 2S master
2003 Apr 10
24
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE 9 Data path:
FEATURES * Input SPDIF to output I2S * Input I2S to outputs DAC or SPDIF. Features: * Possibility to process input SPDIF, via I2S-bus using an external DSP and then to outputs DAC or SPDIF * BCK and WS being master for both I2S input and output (different clocks) * Input I2S to outputs DAC and SPDIF; BCK and WS being master; clocks based on crystal oscillator * Microcontroller mode: - DAC sound features can be used - SPDIF output channel status bits (two times 40) setting.
SPDIF IN I2S INPUT XTAL
SCHEMATIC
PLL
SPDIF LOCK
MUTE DAC
SPDIF OUT I 2S OUTPUT I 2S master
I 2S slave EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715)
MGU845
10
Data path: * Input SPDIF to output DAC or I2S * Input I2S-bus to output SPDIF. Features: * Possibility to process input SPDIF, via I2S-bus using an external DSP and then to output SPDIF * Input SPDIF to outputs I2S and DAC; locking onto the SPDIF input signal; BCK and WS being master * Input I2S to output SPDIF; BCK and WS being master; clocks are generated by the crystal oscillator * Microcontroller mode: - DAC sound features can be used - SPDIF input channel status bits (two times 40) can be read - SPDIF output channel status bits (two times 40) setting.
XTAL PLL
SPDIF LOCK
MUTE DAC SPDIF IN SPDIF OUT I2S INPUT I 2S OUTPUT I 2S master
I 2S slave EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715)
MGU846
11 12 13 14 15
Not used See microcontroller mode See microcontroller mode See microcontroller mode Not used
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
8.3 Microcontroller mode pin assignment
UDA1355H
In microcontroller mode all features become available, such as volume control, PGA gain and mixing (in some modes). The pin functions are defined in Table 12. Table 12 Microcontroller mode pin assignment PIN 4 SYMBOL L3-BUS LOCK SYMBOL I2C-BUS LOCK LEVEL LOW HIGH 16 17 18 19 20 RESET no function A0 U_RDY SEL_STATIC RESET no function A0 U_RDY SEL_STATIC LOW HIGH LOW - LOW HIGH MID LOW HIGH 21 22 29 30 31 44 USER AC3 L3MODE L3CLOCK L3DATA MUTE USER AC3 no function SCL SDA MUTE - LOW HIGH - - - LOW HIGH DESCRIPTION FPLL and SPDIF are out of LOCK FPLL in lock when SPDIF is not used; FPLL or SPDIF in lock when SPDIF is used normal operation reset connect to ground A0 address input/output bit (for microcontroller register) user bit stable new user bit I2C-bus mode L3-bus mode static mode user bit output (new bit every SPDIF sub-frame) no I2S-bus data preamble detected I2S-bus data preamble detected L3MODE for L3-bus mode; no function for I2C-bus L3CLOCK for L3-bus mode or SCL for I2C-bus mode L3DATA for L3-bus mode or SDA for I2C-bus mode no mute mute active
2003 Apr 10
26
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
8.4 Microcontroller mode applications
UDA1355H
In Table 13, the encoding of bits MODE[3:0] in the microcontroller mode is given. Table 13 Microcontroller mode applications MODE BITS MODE MODE[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note 1. In column clock means: xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PLL PLL - xtal PLL PLL xtal xtal PLL SPDIF INPUT PLL - PLL - - - - PLL - PLL PLL SPDIF OUTPUT PLL PLL PLL xtal xtal xtal PLL xtal xtal xtal xtal CLOCK(1) I2S-BUS ADC - - PLL xtal xtal xtal xtal xtal xtal xtal PLL DAC PLL PLL PLL - xtal xtal PLL PLL PLL xtal PLL not used PLL PLL PLL not used PLL PLL PLL xtal xtal PLL SPDIF SPDIF I2S INPUT SLAVE PLL PLL - xtal xtal PLL - PLL xtal xtal I2S-BUS OUTPUT MASTER PLL - PLL xtal xtal xtal xtal xtal xtal PLL PLL PLL LOCKS ON INPUT SPDIF I2S SPDIF - - - I2S SPDIF I2S SPDIF SPDIF
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
In the microcontroller mode, more features are available. The application modes are given in Table 14. Some modes are the same in terms of data path as for the static mode. These modes are already explained in Section 8.2. Some modes are combined into one mode (like modes 4 and 5). Table 14 Overview of microcontroller modes MODE 0 1 2 FEATURE See static mode See static mode Data path: * Inputs ADC, I2S and SPDIF to outputs DAC, I2S or SPDIF. Features: * All clocks are related to the SPDIF clock * I2S input and output have master BCK and WS * SPDIF input channel status bits (two times 40) can be read * Output SPDIF supported but the timing not according to level II: depends on I2S-bus clock * Output SPDIFOUT loop through can be selected with independent SPDIF input channel select.
SPDIF IN SPDIF OUT ADC DAC PLL
SPDIF LOCK
SCHEMATIC
MUTE
SPDIF OUT
I 2S OUTPUT I2S INPUT I 2S slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715)
MGU847
I 2S master
3 4+5
See static mode Data path: * Inputs ADC and I2S to outputs DAC, I2S or SPDIF. Features: * Mode 4 and 5 are combined in microcontroller mode * Crystal oscillator generates the clocks * I2S input and output have master BCK and WS * SPDIF output channel status bits (two times 40) setting.
I2S INPUT SPDIF OUT I 2S OUTPUT ADC DAC XTAL MUTE
I 2S slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715)
I 2S master
MGU848
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE 6 7 8 9
FEATURE See static mode See static mode See static mode Data path: * Inputs ADC and I2S to outputs DAC or SPDIF * Input SPDIF to output I2S. Features: * Input SPDIF to output I2S with BCK and WS being master; the clocks for this are recovered from the SPDIF input signal * The rest of the clocks are generated by the crystal oscillator * SPDIF input channel status bits (two times 40) can be read * SPDIF output channel status bits (two times 40) setting * Possibility to process input SPDIF, via I2S-bus using an external DSP and then to outputs DAC or SPDIF.
XTAL
SCHEMATIC
PLL
SPDIF LOCK
MUTE ADC DAC
SPDIF IN I2S INPUT I2S slave
SPDIF OUT I 2S OUTPUT I2S master
EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715)
MGU849
10
Data path: * Inputs ADC and SPDIF to outputs DAC or I2S * Input I2S to output SPDIF. Features: * BCK and WS are master * SPDIF input channel status bits (two times 40) can be read * SPDIF output channel status bits (two times 40) setting * Possibility to process inputs ADC or SPDIF, via I2S-bus using an external DSP and then to output SPDIF.
SPDIF IN I2S INPUT I 2S slave EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715)
MGU850
XTAL
PLL
SPDIF LOCK
MUTE ADC DAC
SPDIF OUT I 2S OUTPUT I 2S master
11
Not used
2003 Apr 10
29
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE 12 Data path:
FEATURE * Input ADC to outputs I2S or SPDIF * Inputs I2S and SPDIF to output DAC. Features: * BCK and WS of I2S output are master * Inputs SPDIF and I2S to output DAC with mixing/selection possibility; clocks are generated from SPDIF input signal, and BCK and WS are master * SPDIF input channel status bits (two times 40) can be read * SPDIF output channel status bits (two times 40) setting.
I 2S slave ADC XTAL
SCHEMATIC
PLL
SPDIF LOCK
MUTE DAC SPDIF IN SPDIF OUT I2S INPUT I 2S OUTPUT
MGU851
I 2S master
13
Data path: * Input ADC to output I2S * Inputs and SPDIF to outputs DAC or SPDIF. I2S Features * BCK and WS being master * SPDIF input channel status bits (two times 40) can be read * Output SPDIF supported but the timing not according to level II * Output SPDIFOUT loop through can be selected with independent SPDIF input channel select.
I 2S slave I2S INPUT
MGU852
XTAL
PLL
SPDIF LOCK
MUTE ADC DAC
SPDIF IN SPDIF OUT
SPDIF OUT I 2S OUTPUT
I 2S master
14
Data path: * Inputs ADC and I2S to outputs DAC SPDIF and I2S. Features: * All clocks are related to WS signal of I2S-bus input * Master BCK and WS for I2S output; slave BCK and WS for I2S input * SPDIF output channel status bits (two times 40) can be set; level II timing depends on the I2S-bus clocks.
SPDIF OUT I 2S slave I2S INPUT I 2S OUTPUT I 2S master ADC DAC PLL
I 2S LOCK
MUTE
MGU853
15
Not used
2003 Apr 10
30
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
9 9.1 SPDIF SIGNAL FORMAT SPDIF channel encoding 9.2 SPDIF hierarchical layers
UDA1355H
The digital signal is coded using Biphase Mark Code (BMC), which is a kind of phase modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. An example of the encoding is given in Fig.11.
The SPDIF signal format is shown in Fig.12. A PCM signal is transmitted in sequential blocks. Each block consists of 192 frames. Each frame contains two sub-frames, one for each channel. Each subframe is preceded by a preamble. There are three types of preambles: B, M and W. Preambles can be spotted easily in an SPDIF bitstream because these sequences never occur in the channel parts of a valid SPDIF bitstream. The sub-frame format is represented by Fig.13. A sub-frame contains a single audio sample word which may be 24 bits wide, a validity bit which indicates whether the sample is valid, a bit containing user data, a bit indicating the channel status and a parity bit for this sub-frame. The data bits 31 to 4 in each sub-frame are encoded using a BMC scheme. The sync preamble contains a violation of the BMC scheme and can be detected. Table 15 indicates the values of the preambles.
handbook, halfpage
clock
data
BMC
MGU606
Fig.11 Biphase mark encoding.
handbook, full pagewidth
M channel 1 W
channel 2
B
channel 1
W channel 2
M
channel 1
channel 2
M
channel 1
W
channel 2
sub-frame frame 191
sub-frame frame 191 block
MGU607
frame 0
Fig.12 SPDIF signal format
0 handbook, full pagewidth sync preamble
34 L S B auxiliary
78 L S B audio sample word
27 28 M S B validity flag user data channel status parity bit V U C
31 P
MGU608
Fig.13 Sub-frame format
2003 Apr 10
31
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 15 Preambles PRECEDING STATE B M W 9.3 9.3.1 CHANNEL CODING 0 11101000 11100010 11100100 1 00010111 00011101 00011011 9.3.3 DUTY CYCLE
UDA1355H
The duty cycle (see Fig.14) is defined as: tH Duty cycle = --------------- x 100% tL + tH The duty cycle should be in the range: * 40% to 60% when the data bit is a logic 1 * 45% to 55% when the data bits are two succeeding logic 0. 10 L3-BUS DESCRIPTION The exchange of data and control information between the microcontroller and the UDA1355H is accomplished through a serial hardware L3-bus interface comprising the following pins: * MP0: mode line with signal L3MODE * MP1: clock line with signal L3CLOCK * MP2: data line with signal L3DATA. The exchange of bytes in L3-bus mode is LSB first. The L3-bus format has two modes of operation: * Address mode * Data transfer mode. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.15). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. Basically two types of data transfers can be defined: * Write action: data transfer to the device * Read action: data transfer from the device. 10.1 Device addressing
Timing characteristics FREQUENCY REQUIREMENTS
The SPDIF specification IEC 60958 supports three levels of clock accuracy: * Level I high accuracy: Tolerance of transmitting sampling frequency shall be within 50 x 10-6 * Level II, normal accuracy: All receivers should receive a signal of 1000 x 10-6 of nominal sampling frequency * Level III, variable pitch shifted clock mode: A deviation of 12.5% of the nominal sampling frequency is possible. The UDA1355H inputs support level I, II, and III as specified by the IEC 60958 standard. 9.3.2 RISE AND FALL TIMES
Rise and fall times (see Fig.14) are defined as: tr Rise time = --------------- x 100% tL + tH tf Fall time = --------------- x 100% tL + tH Rise and fall times should be in the range: * 0% to 20% when the data bit is a logic 1 * 0% to 10% when the data bits are two succeeding logic 0.
handbook, halfpage
tH
tL
The device address consists of one byte with: * Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 16) * Address bits 2 to 7 representing a 6-bit device address.
90% 50% 10% tr tf
MGU612
Fig.14 Rise, fall time and duty cycle.
2003 Apr 10
32
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 16 Selection of data transfer DOM BITS TRANSFER BIT 0 0 1 0 1 BIT 1 0 0 1 1 not used not used write data or prepare read read data 10.3 Data write mode
UDA1355H
The data write mode is explained in the signal diagram of Fig.15. For writing data to a device, 4 bytes must be sent (see Table 18): * Byte 1 starting with 01 for signalling the write action to the device, followed by the device address * Byte 2 starting with 0 for signalling the write action, followed by 7 bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB * Byte 3 with bit D15 being the MSB * Byte 4 with bit D0 being the LSB. It should be noted that each time a new destination register address needs to be written, the device address must be sent again. 10.4 Data read mode
The device address of the UDA1355H is given in Table 17, being the first 6 bits of the device address byte. The address can be set one of two by using pin MODE1 (pin A0 in microcontroller mode). Table 17 L3-bus device address MSB 0 0 ADDRESS 0 0 1 LSB A0
Remark: When using the device address, there is often misunderstanding. This is caused by the fact that the data is sent LSB first. This means that when we use the device address in, for example the Philips L3-bus/I2C-bus bithacker', we have to use the address like LSB MSB. For the UDA1355H this means that the device address to be used is either 10H (010000) or 30H (110000). 10.2 Register addressing
For reading data from the device, first a prepare read must be done and then data read. The data read mode is explained in the signal diagram of Fig.16. For reading data from a device, the following 6 bytes are involved (see Table 19): * Byte 1 with the device address including 01 for signalling the write action to the device * Byte 2 is sent with the register address from which data needs to be read. This byte starts with 1, which indicates that there will be a read action from the register, followed again by 7 bits for the destination address in binary format with A6 being the MSB and A0 being the LSB * Byte 3 with the device address including 11 is sent to the device. The 11 indicates that the device must write data to the microcontroller * Byte 4, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) * Byte 5, sent by the device to the bus, with the data information in binary format with D15 being the MSB * Byte 6, sent by the device to the bus, with the data information in binary format with D0 being the LSB.
After sending the device address, including Data Operating Mode (DOM) bits indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. Basically there are three methods for register addressing: * Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.15) * Addressing for prepare read: bit 0 is logic 1 indicating that data will be read from the register (see Fig.16) * Addressing for data read action: in this case the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; in case bit 0 is logic 1 the register address is invalid.
2003 Apr 10
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L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 0
MGS753
Philips Semiconductors
Stereo audio codec with SPDIF interface Stereo audio codec with SPDIF interface
register address
data byte 1
data byte 2
DOM bits
write
Fig.15 Data write mode. 34 34
L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2 valid/non-valid send by the device
MGS754
Preliminary specification
UDA1355H UDA1355H
Fig.16 Data read mode.
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 18 L3-bus write data FIRST IN TIME BYTE 1 2 3 4 L3-BUS MODE address data transfer data transfer data transfer ACTION
UDA1355H
LAST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address data byte 1 data byte 2 0 0 D15 D7 1 A6 D14 D6 A0 A5 D13 D5 1 A4 D12 D4 0 A3 D11 D3 0 A2 D10 D2 0 A1 D9 D1 0 A0 D8 D0
Table 19 L3-bus read data FIRST IN TIME BYTE 1 2 3 4 5 6 L3-BUS MODE address data transfer address data transfer data transfer data transfer ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address device address register address data byte 1 data byte 2 0 1 1 0 or 1 D15 D7 11.2 1 A6 1 A6 D14 D6 A0 A5 A0 A5 D13 D5 1 A4 1 A4 D12 D4 0 A3 0 A3 D11 D3 0 A2 0 A2 D10 D2 0 A1 0 A1 D9 D1 0 A0 0 A0 D8 D0 LAST IN TIME
11 I2C-BUS DESCRIPTION 11.1 Characteristics
Bit transfer
The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to the supply voltage (VDD) via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse (see Fig.17). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high speed I2C-bus according the Philips specification.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.17 Bit transfer on the I2C-bus.
2003 Apr 10
35
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
11.3 Byte transfer 11.7 Start and stop conditions
UDA1355H
Each byte (8 bits) is transferred with the MSB first (see Table 20). Table 20 Byte transfer MSB 7 11.4 6 5 4 BIT 3 2 1 LSB 0
Both data and clock line will remain HIGH when the bus in not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P); (see Fig.18). 11.8 Acknowledgment
Data transfer
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. 11.5 Register address
The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.19). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
The register addresses in the I2C-bus mode are the same as in the L3-bus mode. 11.6 Device address I2C-bus,
Before any data is transmitted on the the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The device address can be one of two, being set by bit A0 which corresponds to pin MODE1. The UDA1355H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1355H slave address is shown in Table 21. Table 21 I2C-bus slave address DEVICE ADDRESS A6 0 A5 0 A4 1 A3 1 A2 0 A1 1 A0 A0 R/W - 0/1
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.18 START and STOP conditions on the I2C-bus.
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.19 Acknowledge on the I2C-bus.
11.9
Write cycle
The write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. It is also possible to read these locations for chip status information. The I2C-bus configuration for a write cycle is shown in Table 22. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a couple of two bytes. The format of the write cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1355H.
4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1355H must start. 5. The UDA1355H acknowledges this register address (A). 6. The microcontroller sends two bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1355H. 7. If repeated groups of two bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller. 8. Finally, the UDA1355H frees the I2C-bus and the microcontroller can generate a stop condition (P).
Table 22 Master transmitter writes to the UDA1355H registers in the I2C mode. DEVICE ADDRESS S 0011010 R/W 0 A REGISTER ADDRESS ADDR A MS1 DATA 1 A LS1 A .... DATA 2(1) A ..... A MSn DATA n(1) A LSn A P
acknowledge from UDA1355H Note 1. Auto increment of register address.
2003 Apr 10
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Stereo audio codec with SPDIF interface Stereo audio codec with SPDIF interface
The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 23 The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1355H. 4. After this microcontroller writes the 8-bit register address (ADDR) where the reading of the register content of the UDA1355H must start. 5. The UDA1355H acknowledges this register address (A). 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address 0011010 again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge (A) follows from the UDA1355H. 8. The UDA1355H sends two bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledged follows from the microcontroller. 9. If repeated groups of two bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge follows from the microcontroller. 10. The microcontroller stops this cycle by generating a Negative Acknowledge (NA). 11. Finally, the UDA1355H frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 23 Master transmitter reads from the UDA1355H registers in the I2C-bus mode DEVICE ADDRESS S 0011010 R/W 0 A REGISTER ADDRESS ADDR A Sr acknowledge from UDA1355H Note 1. Auto increment of register address. DEVICE ADDRESS 0011010 R/W 1 A DATA 1 MS1 A LS1 DATA 2(1) DATA n(1) LSn NA P
A ... A ... A MSn A acknowledge from master
Preliminary specification
UDA1355H UDA1355H
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
12 REGISTER MAPPING
UDA1355H
In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the mapping of the readable and writable registers is given. The explanation of the register definitions are explained in Sections 12.2 and 12.3. 12.1 Address mapping
Table 24 Register map settings ADDRESS R/W DESCRIPTION
System settings 00H 01H 02H 03H 04H Interpolator 10H 11H 12H 13H 14H 18H 19H 1AH 1BH 1CH 1DH 1EH Decimator 20H 21H 22H 28H SPDIF input 30H 40H 59H 5AH 5BH 5CH R/W R/W R R R R SPDIF power control and SPDIF input settings reserved for manufacturers evaluation and should be kept untouched for normal operation SPDIF LOCK; bit error information and SPDIF encoder output status read-out SPDIF input status bits 15 to 0 left channel read-out SPDIF input status bits 31 to 16 left channel read-out SPDIF input status bits 39 to 32 left channel read-out R/W R/W R/W R ADC gain settings ADC mute and PGA gain settings; ADC polarity and DC cancellation settings mute status and overflow ADC read-out R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W master volume control settings mixer volume settings sound feature and bass boost and treble settings gain select; de-emphasis and mute settings DAC polarity; noise shaper selection; mixer; source selection; silence detector and interpolator oversampling settings mute and silence detector status read-out resonant bass boost coefficient k1 setting resonant bass boost coefficient km setting resonant bass boost coefficient a1 setting resonant bass boost coefficient a2 setting resonant bass boost coefficient b1 setting resonant bass boost coefficient b2m setting R/W R/W R/W R/W R/W crystal clock power-on setting; crystal clock and PLL divider settings; MODE and WS detector settings; clock output setting I2S-bus output format settings I2S-bus input format settings reserved for manufacturers evaluation and should be kept untouched for normal operation analog power and clock settings
2003 Apr 10
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
ADDRESS 5DH 5EH 5FH SPDIF output 50H 51H 52H 53H 54H 55H 56H 60H 61H 62H 63H 64H Device ID 7EH
R/W R R R
DESCRIPTION SPDIF input status bits 15 to 0 right channel read-out SPDIF input status bits 31 to 16 right channel read-out SPDIF input status bits 39 to 32 right channel read-out
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SPDIF output valid; left to right channel status bit copy; power control and SPDIF output selection setting SPDIF output status bits 39 to 24 left channel setting SPDIF output status bits 23 to 8 left channel setting SPDIF output status bits 7 to 0 left channel setting SPDIF output status bits 39 to 24 right channel setting SPDIF output status bits 23 to 8 right channel setting SPDIF output status bits 7 to 0 right channel setting reserved for manufacturers evaluation and should be kept untouched for normal operation reserved for manufacturers evaluation and should be kept untouched for normal operation reserved for manufacturers evaluation and should be kept untouched for normal operation reserved for manufacturers evaluation and should be kept untouched for normal operation reserved for manufacturers evaluation and should be kept untouched for normal operation
R
device ID; version
Software reset 7FH 12.2 12.2.1 R/W restore L3-bus defaults
Read/write registers mapping SYSTEM SETTINGS
Table 25 Register address 00H BIT Symbol Default BIT Symbol Default 15 EXPU 0 7 MODE3 0 14 - 0 6 MODE2 0 13 12 11 XTL_DIV3 1 3 ws_detct_EN 1 10 XTL_DIV2 0 2 ws_detct_set 0 9 XTL_DIV1 0 1 CLKOUT_ SEL1 1 8 XTL_DIV0 0 0 CLKOUT_ SEL0 0
PON_XTAL XTL_DIV4 PLL 1 5 MODE1 1 0 4 MODE0 0
2003 Apr 10
40
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 26 Description of register bits (address 00H) BIT 15 14 13 SYMBOL EXPU - PON_XTALPLL DESCRIPTION
UDA1355H
EXPU. Bit EXPU is reserved for manufacturers evaluation and should be kept untouched for normal operation of UDA1355H. reserved Power control crystal oscillator and PLL. If this bit is logic 0, then the crystal oscillator and PLL are turned off; if this bit is logic 1, then the crystal oscillator and PLL are running. Crystal oscillator clock divider setting. Value to select the sampling frequency and the system clock output frequency (256fs or 384fs). When 256fs is selected, the master BCKI and BCKO clock frequency of digital interface running with crystal oscillator clock will be 64fs; when 384fs is selected, it will be 48fs (see Table 27). Microcontroller application mode setting. Value to select the microcontroller application mode (see Table 28). Word select detector enable.If this bit is logic 0, then WS detector is disabled; if this bit is logic 1, then WS detector is enabled. Word select detector limit setting. If this bit is logic 0, then the lower frequency limit of the WS detector is 4095 clock cycles (3 kHz); if this bit is logic 1, then the lower frequency limit of the WS detector is 2047 clock cycles (6 kHz).
12 to 8
XTL_DIV[4:0]
7 to 4 3 2
MODE[3:0] ws_detct_EN ws_detct_set
1 and 0 CLKOUT_SEL[1:0] Clock output select. If these bits are 00 or 10, then the BCKI and BCKO clock frequency of digital interface running with FPLL clock will be 64fs; otherwise, it will be 48fs. The selection between 256fs and 384fs for the crystal clock output is set via the bits XTL_DIV[4:0]: 00 = FPLL clock 256fs 01 = FPLL clock 384fs 10 = crystal clock 11 = crystal clock Table 27 Crystal oscillator output frequencies XTL_DIV4 Based on 32 kHz 0 0 0 0 0 0 Based on 44.1 kHz 0 0 0 0 0 0 2003 Apr 10 0 0 1 1 1 1 1 1 0 0 0 0 41 1 1 0 0 1 1 0 1 0 1 0 1 256 x 22.05 kHz 384 x 22.05 kHz 256 x 44.1 kHz 384 x 44.1 kHz 256 x 88.2 kHz 384 x 88.2 kHz 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 256 x 16 kHz 384 x 16 kHz 256 x 32 kHz 384 x 32 kHz 256 x 64 kHz 384 x 64 kHz XTL_DIV3 XTL_DIV2 XTL_DIV1 XTL_DIV0 OUTPUT RATE
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
XTL_DIV4 Based on 48 kHz 0 0 0 0 1 1
XTL_DIV3
XTL_DIV2
XTL_DIV1
XTL_DIV0
OUTPUT RATE 256 x 24 kHz 384 x 24 kHz 256 x 48 kHz 384 x 48 kHz 256 x 96 kHz 384 x 96 kHz
1 1 1 1 0 0
1 1 1 1 0 0
0 0 1 1 0 0
0 1 0 1 0 1
Table 28 Application mode selection MODE3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 29 Register address 01H BIT Symbol Default BIT Symbol Default 15 - 0 7 PON_DIGO 1 14 - 0 6 - 0 13 - 0 5 DIGOUT1 1 12 - 0 4 DIGOUT0 0 11 - 0 3 - 0 10 - 0 2 SFORO2 0 9 - 0 1 SFORO1 0 8 MUTE_DAO 0 0 SFORO0 0 MODE2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MODE1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MODE0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode 8 mode 9 mode 10 mode 11 mode 12 mode 13 mode 14 mode 15
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 30 Description of register bits (address 01H) BIT 15 to 9 8 7 - MUTE_DAO PON_DIGO SYMBOL reserved DESCRIPTION
UDA1355H
Digital mute setting. If this bit is logic 0, then the digital output is not muted; if this bit is logic 1, then the digital output is muted. Power control digital output. If this bit is logic 0, then the digital output is in Power-down mode; if this bit is logic 1, then the digital output is in power-on mode. The registers have their own clock, which means that there cannot be a dead-lock situation. reserved Input selector for digital output. Value to select the input signal for the digital output. The default input will be chosen if in an application an invalid data signal is selected: 00 = ADC input 01 = digital input 10 = IEC 60958 input 11 = interpolator mixer output
6
-
5 and 4 DIGOUT[1:0]
3 2 to 0
- SFORO[2:0]
reserved Digital output format. Value to set the digital output format: 000 = I2S-bus 001 = LSB-justified; 16 bits 010 = LSB-justified; 18 bits 011 = LSB-justified; 20 bits 100 = LSB-justified; 24 bits 101 = MSB-justified 110 = not used; output is default value 111 = not used; output is default value
Table 31 Register address 02H BIT Symbol Default BIT Symbol Default 15 - 0 7 PON_DIGI 1 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 - 0 3 - 0 10 - 0 2 SFORI2 0 9 - 0 1 SFORI1 0 8 - 0 0 SFORI0 0
Table 32 Description of register bits (address 02H) BIT 15 to 8 7 - PON_DIGI SYMBOL reserved Power control digital input. If this bit is logic 0, then the digital input is in Power-down mode; if this bit is logic 1, then the digital input is in power-on mode. The registers have their own clock, which means that there cannot be a dead-lock situation. reserved DESCRIPTION
6 to 3
-
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
BIT 2 to 0
SYMBOL SFORI[2:0] 000 = I2S-bus 001 = LSB-justified; 16 bits 010 = LSB-justified; 18 bits 011 = LSB-justified; 20 bits 100 = LSB-justified; 24 bits 101 = MSB-justified
DESCRIPTION Digital input format. Value to set the digital input format:
110 = not used; input is default value 111 = not used; input is default value Table 33 Register address 04H BIT Symbol Default BIT Symbol Default 15 PON_DAC 1 7 DACLK_OFF 0 14 - 0 6 DACLK_AUTO 0 13 - 0 5 - 0 12 - 0 4 - 0 11 - 0 3 - 0 10 1 2 EN_DEC 1 9 1 1 - 0 8 1 0 EN_INT 1
PON_ADCL PON_ADCR PON_ADC_bias
Table 34 Description of register bits (address 04H) BIT 15 SYMBOL PON_DAC DESCRIPTION Power control DAC. If this bit is logic 0, then the DAC is in Power-down mode; if this bit is logic 1, then the DAC is in power-on mode. This bit is only connected to the DAC input and is not combined with mute status or other signals. reserved Power control ADC left channel. Value to set power on the ADC left channel (see Table 35). Power control ADC right channel. Value to set power on the ADC right channel (see Table 35). Power control ADC bias. Value to set power on the ADCs (see Table 35). DAC clock enable. If this bit is logic 0, then the DAC clock is disabled; if this bit is logic 1, then the DAC clock is enabled. DAC clock auto function. If this bit is logic 0, then the DAC clock auto function is disabled; if this bit is logic 1, then the DAC clock auto function is enabled. If the FPLL is unlocked, the interpolator will be muted and the DAC clock is automatically disabled. reserved Decimator and ADC clock enable. If this bit is logic 0, then the clock to decimator and ADC is disabled; if this bit is logic 1, then the clock to decimator and ADC is running. reserved Interpolator clock enable. If this bit is logic 0, then the clock to interpolator and FSDAC is disabled; if this bit is logic 1, then the clock to the interpolator and FSDAC is running.
14 to 11 - 10 9 8 7 6 PON_ADCL PON_ADCR PON_ADC_bias DACLK_OFF DACLK_AUTO
5 to 3 2 1 0
- EN_DEC - EN_INT
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Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
Table 35 ADC power control PON_ADC_BIAS 0 1 1 1 1 12.2.2 INTERPOLATOR PON_ADCR X 0 1 0 1 PON_ADCL X 0 0 1 1 DESCRIPTION no power on both ADCs no power on both ADCs only power on right channel ADC only power on left channel ADC power on both ADCs
UDA1355H
Table 36 Register address 10H BIT Symbol Default BIT Symbol Default 15 MVCL_7 0 7 MVCR_7 0 14 MVCL_6 0 6 MVCR_6 0 13 MVCL_5 0 5 MVCR_5 0 12 MVCL_4 0 4 MVCR_4 0 11 MVCL_3 0 3 MVCR_3 0 10 MVCL_2 0 2 MVCR_2 0 9 MVCL_1 0 1 MVCR_1 0 8 MVCL_0 0 0 MVCR_0 0
Table 37 Description of register bits (address 10H) BIT 15 to 8 7 to 0 SYMBOL MVCL_[7:0] MVCR_[7:0] DESCRIPTION Master volume setting left channel. Value to program the left channel master volume attenuation. The range is 0 dB to -78 dB and dB (see Table 38). Master volume setting right channel. Value to program the right channel master volume attenuation. The range is 0 dB to -78 dB and dB (see Table 38).
Table 38 Master volume setting left and right channel MVCL_7 MVCR_7 0 0 0 0 0 : 1 1 1 1 1 MVCL_6 MVCR_6 0 0 0 0 0 : 1 1 1 1 1 MVCL_5 MVCR_5 0 0 0 0 0 : 0 0 0 0 0 MVCL_4 MVCR_4 0 0 0 0 0 : 0 0 0 0 1 MVCL_3 MVCR_3 0 0 0 0 0 : 1 1 1 1 0 MVCL_2 MVCR_2 0 0 0 0 1 : 1 1 1 1 0 MVCL_1 MVCR_1 0 0 1 1 0 : 0 0 1 1 0 MVCL_0 VOLUME (dB) MVCR_0 0 1 0 1 0 : 0 1 0 1 0 0 -0.25 -0.5 -0.75 -1 : -51 -51.25 -51.5 -51.75 -52
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Stereo audio codec with SPDIF interface
UDA1355H
MVCL_7 MVCR_7 1 1 : 1 1 1 1 1
MVCL_6 MVCR_6 1 1 : 1 1 1 1 1
MVCL_5 MVCR_5 0 0 : 1 1 1 1 1
MVCL_4 MVCR_4 1 1 : 0 1 1 1 1
MVCL_3 MVCR_3 0 1 : 1 0 0 1 1
MVCL_2 MVCR_2 1 0 : 1 0 1 0 1
MVCL_1 MVCR_1 0 0 : 0 0 0 0 0
MVCL_0 VOLUME (dB) MVCR_0 0 0 : 0 0 0 0 0 -54 -56 : -66 -69 -72 -78 -
Table 39 Register address 11H BIT Symbol Default BIT Symbol Default 15 VC2_7 1 7 VC1_7 0 14 VC2_6 1 6 VC1_6 0 13 VC2_5 1 5 VC1_5 0 12 VC2_4 1 4 VC1_4 0 11 VC2_3 1 3 VC1_3 0 10 VC2_2 1 2 VC1_2 0 9 VC2_1 1 1 VC1_1 0 8 VC2_0 1 0 VC1_0 0
Table 40 Description of register bits (address 11H) BIT 15 to 8 7 to 0 SYMBOL VC2_[7:0] VC1_[7:0] DESCRIPTION Mixer volume setting channel 2. Value to program channel 2 mixer volume attenuation. The range is 0 dB to -72 dB and dB (see Table 41). Mixer volume setting channel 1. Value to program channel 1 mixer volume attenuation. The range is 0 dB to -72 dB and dB (see Table 41).
Table 41 Mixer volume setting channel 1 and 2 VC2_7 VC1_7 0 0 0 0 0 : 1 1 1 1 1 VC2_6 VC1_6 0 0 0 0 0 : 0 0 0 0 0 VC2_5 VC1_5 0 0 0 0 0 : 1 1 1 1 1 VC2_4 VC1_4 0 0 0 0 0 : 1 1 1 1 1 VC2_3 VC1_3 0 0 0 0 0 : 0 0 0 0 1 VC2_2 VC1_2 0 0 0 0 1 : 1 1 1 1 0 VC2_1 VC1_1 0 0 1 1 0 : 0 0 1 1 0 VC2_0 VOLUME (dB) VC1_0 0 1 0 1 0 : 0 1 0 1 0 0 -0.25 -0.5 -0.75 -1 : -45 -45.25 -45.5 -45.75 -46
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Stereo audio codec with SPDIF interface
UDA1355H
VC2_7 VC1_7 1 1 : 1 1 1 1 1 : 1
VC2_6 VC1_6 0 1 : 1 1 1 1 1 : 1
VC2_5 VC1_5 1 0 : 0 0 0 1 1 : 1
VC2_4 VC1_4 1 0 : 1 1 1 0 0 : 1
VC2_3 VC1_3 1 0 : 0 1 1 0 0 : 1
VC2_2 VC1_2 1 0 : 1 0 1 0 1 : 1
VC2_1 VC1_1 0 0 : 0 0 0 0 0 : 0
VC2_0 VOLUME (dB) VC1_0 0 0 : 0 0 0 0 0 : 0 -48 -50 : -60 -63 -66 -72 - : -
Table 42 Register address 12H BIT Symbol Default BIT Symbol Default 15 M1 0 7 BB_OFF 0 14 M0 0 6 BB_FIX 0 13 TRL1 0 5 TRR1 0 12 TRL0 0 4 TRR0 0 11 BBL3 0 3 BBR3 0 10 BBL2 0 2 BBR2 0 9 BBL1 0 1 BBR1 0 8 BBL0 0 0 BBR0 0
Table 43 Description of register bits (address 12H) BIT 15 and 14 SYMBOL M[1:0] DESCRIPTION Sound feature mode. Value to program the sound processing filter sets (modes) of bass boost and treble: 00 = flat set 01 = minimum set 10 = minimum set 11 = maximum set 13 and 12 TRL[1:0] Treble settings left. Value to program the left channel treble setting. Both left and right channels will follow the left channel setting when bit BASS_SEL = 1. The used filter set is selected with the sound feature mode bits M1 and M2 (see Table 44). Normal bass boost settings left. Value to program the left bass boost settings. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 45). Resonant bass boost. If this bit is logic 0 then the resonant bass boost is enabled; if this bit is logic 1 then the resonant bass boost is disabled.
11 to 8 7
BBL[3:0] BB_OFF
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Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
BIT 6
SYMBOL BB_FIX
DESCRIPTION Resonant bass boost coefficient. If this bit is logic 0 then the resonant bass boost coefficient is finished loading; if this bit is logic 1 then the resonant bass boost coefficient is loading to register. Treble settings right. Value to program the right treble setting. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 44). Normal bass boost settings right. Value to program the right bass boost settings. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 45).
5 and 4 3 to 0
TRR[1:0] BBR[3:0]
Table 44 Treble settings TRL1 TRR1 0 0 1 1 TRL0 FLAT SET (dB) TRR0 0 1 0 1 0 0 0 0 0 2 4 6 0 2 4 6 MIN. SET (dB) MAX. SET (dB)
Table 45 Normal bass boost settings; note 1 BBL3 BBR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. The bass boost setting is only effective when bit BASS_SEL = 0. BBL2 BBR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BBL1 BBR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BBL0 FLAT SET (dB) BBR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24 MIN SET (dB) MAX SET (dB)
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Stereo audio codec with SPDIF interface
Table 46 Register address 13H BIT Symbol Default BIT Symbol Default 15 - 0 7 MTNS1 0 14 MTM 0 6 MTNS0 0 13 GS 0 5 WS_SEL 0 12 MIXGAIN 0 4 DE_SW 0 11 MT2 1 3 MT1 0 10 DE2_2 0 2 DE1_2 0
UDA1355H
9 DE2_1 0 1 DE1_1 0
8 DE2_0 0 0 DE1_0 0
Table 47 Description of register bits (address 13H) BIT 15 14 13 12 11 10 to 8 7 and 6 MTM GS MIXGAIN MT2 DE2_[2:0] MTNS[1:0] SYMBOL reserved Master mute. If this bit is logic 0 then there is no master mute or the master de-mute is in progress; if this bit is logic 1 then the master mute is in progress or muted. Gain select. See Table 48. Mixer gain select. See Tables 48 and 49. Channel 2 mute. If this bit is logic 0 then channel 2 is not muted or the de-mute is in progress; if this bit is logic 1 then channel 2 is muted or the muting is in progress. De-emphasis setting for channel 2. See Table 50. Interpolator mute. Selection: 00 = no mute 01 = if no WS signal is detected, the noise shaper of the interpolator mute 1x = the noise shaper of the interpolator mute 5 4 3 2 to 0 WS_SEL DE_SW MT1 DE1_[2:0] WS signal select. If this bit is logic 0 then WS_DET is selected for the WS detection; if this bit is logic 1 then FPLL is selected for the WS detection. De-emphasis select. If this bit is logic 0 then SPDIF pre-emphasis information is selected; if this bit is logic 1 then the de-emphasis setting is selected. Channel 1 mute. If this bit is logic 0 then channel 1 is not muted or the de-mute is in progress; if this bit is logic 1 then channel 1 is muted or the muting is in progress. De-emphasis setting for channel 1. See Table 50. DESCRIPTION
Table 48 DAC gain setting GS 0 1 1 1 1 Notes 1. See Table 52. 2. X = don't care MIX(1) X(2) 0 1 0 1 MIX_GAIN X(2) 0 0 1 1 DAC GAIN (dB) 0 6 0 6 6
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 49 Mixer gain setting MIX(1) 1 1 Note 1. See Table 52. Table 50 De-emphasis setting for the incoming signal DE2_2 DE1_2 0 0 0 0 1 Table 51 Register address 14H BIT Symbol Default BIT Symbol Default 15 DA_POL_ INV 0 7 SILENCE 0 14 SEL_NS 1 6 SDET_ON 0 13 MIX_POS 0 5 SD_ VALUE1 0 12 MIX 0 4 SD_ VALUE0 0 11 10 9 DE2_1 DE1_1 0 0 1 1 0 DE2_0 FUNCTION DE1_0 0 1 0 1 0 off 32 kHz 44.1 kHz 48 kHz 96 kHz MIX_GAIN 0 1 MIXER OUTPUT GAIN
UDA1355H
DAC output gain is set to 0 dB and mixer signal output gain is set -6 dB DAC output gain and mixer signal output gain are set to 0 dB
8
DAC_CH2_ DAC_CH2_ DAC_CH1_ DAC_CH1_ SEL1 SEL0 SEL1 SEL0 1 3 BASS_SEL 0 1 2 BYPASS 0 0 1 OS_IN1 0 1 0 OS_IN0 0
Table 52 Description of register bits (address 14H) BIT 15 14 13 12 11 and 10 SYMBOL DA_POL_INV SEL_NS MIX_POS MIX DAC_CH2_SEL[1:0] DESCRIPTION DAC polarity control. If this bit is logic 0 then the DAC output is not inverted; if this bit is logic 1 then the DAC output is inverted. Select noise shaper. If this bit is logic 0 then the third order noise shaper is selected; if this bit is logic 1 then the fifth order noise shaper is selected. Mixer position. Mixing is done before or after the sound processing unit (see Table 53). Mixer. If this bit is logic 0 then the mixer is disabled; if this bit is logic 1 then the mixer is enabled (see Tables 48, 49 and 53). DAC channel 2 input selection. Value to select the input mode to channel 2 of the interpolator (see Table 54). DAC channel 1 input selection. Value to select the input mode to channel 1 of the interpolator (see Table 54).
9 and 8 DAC_CH1_SEL[1:0]
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Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
BIT 7
SYMBOL SILENCE
DESCRIPTION Silence detector overrule. Value to force the DAC output to silence. This will give a plop at the output of the DAC because of mismatch in offsets and the DC offset added to the signal in the interpolator itself. If this bit is logic 0 then there is no overruling and the FSDAC silence switch setting depends on the silence detector circuit and on the status of bit MTM; if this bit is logic 1 then there is overruling and the FSDAC silence switch is activated independent of the status of the digital silence detector circuit or the status of bit MTM. Silence detector enable. If this bit is logic 0 then the silence detection circuit is disabled; if this bit is logic 1 then the silence detection circuit is enabled. Silence detector setting. Value to program the silence detector. The number of zero samples counted before the silence detector signals whether there has been digital silence: 00 = 3200 samples 01 = 4800 samples 10 = 9600 samples 11 = 19200 samples
6
SDET_ON
5 and 4 SD_VALUE[1:0]
3 2
BASS_SEL BYPASS
Bass boost select. If this bit is logic 0 then the normal bass boost function is selected; if this bit is logic 1 then the resonant bass boost function is selected. Mixer bypass mode. If this bit is logic 0 then the mixer is in mixer mode; if this bit is logic 1 then the mixer is in mixer bypass mode. Oversampling ratio select. Value to select the oversampling input mode. This mode is only for I2S-bus input: 00 = single speed input; normal input; mixing possible 01 = double speed input; after first half-band filter; no mixing possible but volume and mute still possible 10 = quad speed input; in front of noise shaper; no mixing possible; no volume control possible 11 = reserved.
1 and 0 OS_IN[1:0]
Table 53 Mixer signal control signals MIX 0 1 MIX_POS X(1) 0 FUNCTION this is the default setting: no mixing, volume of channel 1 is forced to 0 dB and volume of channel 2 is forced to - dB mixing is done before the sound processing; input signals are automatically scaled by 6 dB in order to prevent clipping during adding; after the addition, the 6 dB scaling is compensated mixing is done after the sound processing; input signals are automatically scaled in order to prevent clipping during adding
1 Note 1. X = don't care
1
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 54 Data source selector DAC channel 1 and 2; note 1 DAC_CH2_SEL1 DAC_CH1_SEL1 0 0 1 1 Note DAC_CH2_SEL0 DATA OUTPUT DAC DAC_CH1_SEL0 0 1 0 1 ADC input I2S-bus input IEC 60958 input I2S-bus input
UDA1355H
1. The change of the data source will take place only when the mix mode is turned on (bit MIX = 1). The channel 2 input selection is valid only when the channel 1 data source is correct. Table 55 Register addresses 19H, 1AH, 1BH, 1CH, 1DH and 1EH BIT Symbol Default BIT Symbol Default 15 - 0 7 0 14 - 0 6 0 13 0 5 BASS_x_5 0 12 0 4 BASS_x_4 0 11 0 3 BASS_x_3 0 10 0 2 BASS_x_2 0 9 0 1 0 8 0 0 0
BASS_x_13 BASS_x_12 BASS_x_11 BASS_x_10 BASS_x_9 BASS_x_8
BASS_x_7 BASS_x_6
BASS_x_1 BASS_x_0
Table 56 Description of register bits (addresses 19H, 1AH, 1BH, 1CH, 1DH and 1EH) BIT 15 and 14 - 13 to 0 BASS_x_[13:0] SYMBOL reserved Resonant bass boost coefficient x. Six 14-bit registers are used as the filter coefficients to specify the bass boost characteristics. The six coefficients are k1, km, a1, a2, b1 and b2m. A software program is available for users to generate these six 14-bit coefficients by entering the desired centre frequency, peak gain, sampling frequency and shape factor (default flat response). DESCRIPTION
12.2.3
DECIMATOR SETTINGS
Table 57 Register address 20H BIT Symbol Default BIT Symbol Default 15 MA_ DECL7 0 7 MA_ DECR7 0 14 MA_ DECL6 0 6 MA_ DECR6 0 13 MA_ DECL5 0 5 MA_ DECR5 0 12 MA_ DECL4 0 4 MA_ DECR4 0 11 MA_ DECL3 0 3 MA_ DECR3 0 10 MA_ DECL2 0 2 MA_ DECR2 0 9 MA_ DECL1 0 1 MA_ DECR1 0 8 MA_ DECL0 0 0 MA_ DECR0 0
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 58 Description of register bits (address 20H) BIT 15 to 8 7 to 0 SYMBOL MA_DECL[7:0] MA_DECR[7:0] DESCRIPTION
UDA1355H
ADC volume setting left channel. Value to program the ADC gain setting for the left channel. The range is from +24 to -63 dB and - dB (see Table 59). ADC volume setting right channel. Value to program the ADC gain setting for the right channel. The range is from +24 to -63 dB and - dB (see Table 59).
Table 59 ADC volume control settings MA_ DECL7 MA_ DECR7 0 0 0 : 0 0 0 1 : 1 1 1 1 1 MA_ DECL6 MA_ DECR6 0 0 0 : 0 0 0 1 : 0 0 0 0 0 MA_ DECL5 MA_ DECR5 1 1 1 : 0 0 0 1 : 0 0 0 0 0 MA_ DECL4 MA_ DECR4 1 0 0 : 0 0 0 1 : 0 0 0 0 0 MA_ DECL3 MA_ DECR3 0 1 1 : 0 0 0 1 : 0 0 0 0 0 MA_ DECL2 MA_ DECR2 0 1 1 : 0 0 0 1 : 1 0 0 0 0 MA_ DECL1 MA_ DECR1 0 1 1 : 1 0 0 1 : 0 1 1 0 0 MA_ DECL0 GAIN (dB) MA_ DECR0 0 1 0 : 0 1 0 1 : 0 1 0 1 0 +24.0 +23.5 +23.0 : +1.0 +0.5 0 -0.5 : -62.0 -62.5 -63.0 -63.5 -
Table 60 Register address 21H BIT Symbol Default BIT Symbol Default 15 MT_ADC 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 10 9 8
PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ CTRLL3 CTRLL2 CTRLL1 CTRLL0 0 3 0 2 0 1 0 0
PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ CTRLR3 CTRLR2 CTRLR1 CTRLR0 0 0 0 0
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 61 Description of register bits (address 21H) BIT 15 SYMBOL MT_ADC DESCRIPTION
UDA1355H
Mute ADC. If this bit is logic 0 then the ADC is not muted; if this bit is logic 1 then the ADC is muted. reserved PGA gain control left channel. Value to program the gain of the left input amplifier. There are nine settings (see Table 62). reserved PGA gain control right channel. Value to program the gain of the right input amplifier. There are nine settings (see Table 62).
14 to 12 - 11 to 8 7 to 4 3 to 0 PGA_GAIN_CTRLL[3:0] - PGA_GAIN_CTRLR[3:0]
Table 62 ADC input amp PGA gain settings PGA_GAIN_ CTRLL3 PGA_GAIN_ CTRLR3 0 0 0 0 0 0 0 0 1 Table 63 Register address 22H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 ADCPOL_INV 0 4 - 0 11 - 0 3 - 0 10 - 0 2 - 0 9 - 0 1 DC_SKIP 1 8 - 0 0 HP_EN_DEC 1 PGA_GAIN_ CTRLL2 PGA_GAIN_ CTRLR2 0 0 0 0 1 1 1 1 0 PGA_GAIN_ CTRLL1 PGA_GAIN_ CTRLR1 0 0 1 1 0 0 1 1 0 PGA_GAIN_ CTRLL0 GAIN (dB) PGA_GAIN_ CTRLR0 0 1 0 1 0 1 0 1 0 0 3 6 9 12 15 18 21 24
Table 64 Description of register bits (address 22H) BIT 15 to 13 - 12 ADCPOL_INV SYMBOL reserved ADC polarity control. If this bit is logic 0 then the ADC input is not inverted; if this bit is logic 1 then the ADC input is inverted. DESCRIPTION
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Stereo audio codec with SPDIF interface
UDA1355H
BIT 11 to 2 1 -
SYMBOL reserved DC_SKIP
DESCRIPTION DC filter skip. If this bit is logic 0 then the DC filter is enabled; if this bit is logic 1 then the DC filter is disabled. The DC filter is at the output of the comb filter just before the decimator. This DC filter compensates for the DC offset added in the ADC (to remove idle tones from the audio band). This DC offset must not be amplified in order to prevent clipping. High-pass enable. If this bit is logic 0 then the high-pass is disabled; if this bit is logic 1 then the high-pass is enabled. The high-pass is a DC filter which is at the output of the decimation filter (running at fs).
0
HP_EN_DEC
12.2.4
SPDIF INPUT SETTINGS
Table 65 Register address 30H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 PON_SPDI 1 11 - 0 3 - 0 10 - 0 2 - 0 9 - 0 1 SLICER_SEL1 0 8 - 0 0 SLICER_SEL0 0
Table 66 Description of register bits (address 30H) BIT 15 to 5 4 - PON_SPDI SYMBOL reserved Power control SPDIF input. If this bit is logic 0 then the SPDIF input is switched to Power-down mode; if this bit is logic 1 then the SPDIF input is switched to power-on mode. reserved 00 = IEC 60958 input from pin SPDIF0 01 = IEC 60958 input from pin SPDIF1 10 = IEC 60958 input from pin SPDIF2 11 = IEC 60958 input from pin SPDIF3 DESCRIPTION
3 and 2 -
1 and 0 SLICER_SEL[1:0] SPDIF source select. Value to select an IEC 60958 input channel:
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Stereo audio codec with SPDIF interface
12.2.5 SPDIF OUTPUT SETTINGS
UDA1355H
Table 67 Register address 50H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 L_r_copy 1 13 - 0 5 - 0 12 - 0 4 1 11 - 0 3 0 10 - 0 2 1 9 - 0 1 0 8 SPDO_ VALID 0 0 0
PON_SPDO DIS_SPDO SPDOUT_SEL2 SPDOUT_SEL1 SPDOUT_SEL0
Table 68 Description of register bits (address 50H) BIT 15 to 9 - 8 7 6 SPDO_VALID - L_r_copy SYMBOL reserved SDPDIF output valid. If this bit is logic 0 then the SPDIF output is invalid; if this bit is logic 1 then the SPDIF output is valid. reserved SPDIF channel status copy. If this bit is logic 0 then the status bits of the left channel are not copied to the right channel; if this bit is logic 1 then the status bits of the left channel are copied to the right channel. reserved Power control of SPDIF output. If this bit is logic 0 then the SPDIF output is switched to Power-down mode; if this bit is logic 1 then the SPDIF output is switched to power-on mode. SPDIF encoder enable. If this bit is logic 0 then the SPDIF encoder is enabled; if this bit is logic 1 then the SPDIF encoder is disabled. SPDIF output source selector. Value to select the input source for SPDIF output. The selection option to select the SPDIF input just after the slicer was already there. Added is an independent selection of the input signals SPDIF0 to SPDIF3: 000 = ADC 001 = I2S-bus input 010 = not used 011 = interpolator mix output 100 = SPDIF0 loop through 101 = SPDIF1 loop through 110 = SPDIF2 loop through 111 = SPDIF3 loop through DESCRIPTION
5 4
- PON_SPDO
3 2 to 0
DIS_SPDO SPDOUT_SEL[2:0]
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 69 Register addresses 51H (left) and 54H (right) BIT Symbol Default BIT Symbol Default 15 SPDO_ BIT39 0 7 SPDO_ BIT31 0 14 SPDO_ BIT38 0 6 SPDO_ BIT30 0 13 SPDO_ BIT37 0 5 SPDO_ BIT29 0 12 SPDO_ BIT36 0 4 SPDO_ BIT28 0 11 SPDO_ BIT35 0 3 SPDO_ BIT27 0 10 SPDO_ BIT34 0 2 SPDO_ BIT26 0
UDA1355H
9 SPDO_ BIT33 0 1 SPDO_ BIT25 0
8 SPDO_ BIT32 0 0 SPDO_ BIT24 0
Table 70 Register addresses 52H (left) and 55H (right) BIT Symbol Default BIT Symbol Default 15 SPDO_ BIT23 0 7 SPDO_ BIT15 0 14 SPDO_ BIT22 0 6 SPDO_ BIT14 0 13 SPDO_ BIT21 0 5 SPDO_ BIT13 0 12 SPDO_ BIT20 0 4 SPDO_ BIT12 0 11 SPDO_ BIT19 0 3 SPDO_ BIT11 0 10 SPDO_ BIT18 0 2 SPDO_ BIT10 0 9 SPDO_ BIT17 0 1 SPDO_ BIT9 0 8 SPDO_ BIT16 0 0 SPDO_ BIT8 0
Table 71 Register addresses 53H (left) and 56H (right) BIT Symbol Default BIT Symbol Default 15 - 0 7 SPDO_ BIT7 0 14 - 0 6 SPDO_ BIT6 0 13 - 0 5 SPDO_ BIT5 0 12 - 0 4 SPDO_ BIT4 0 11 - 0 3 SPDO_ BIT3 0 10 - 0 2 SPDO_ BIT2 0 9 - 0 1 SPDO_ BIT1 0 8 - 0 0 SPDO_ BIT0 0
Table 72 Description of register bits BIT 39 to 36 35 to 33 32 SYMBOL SPDO_BIT[39:36] SPDO_BIT[35:33] SPDO_BIT[32] reserved Word length. Value indicating the word length (see Table 73). Audio sample word length. Value to signal the maximum audio sample word length. If bit 32 is logic 0, then the maximum length is 20 bits; if bit 32 is logic 1, then the maximum length is 24 bits (see Table 73). reserved DESCRIPTION
31 to 30
SPDO_BIT[31:30]
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Stereo audio codec with SPDIF interface
UDA1355H
BIT 29 to 28
SYMBOL SPDO_BIT[29:28] 00 = level II 01 = level I 10 = level III 11 = reserved
DESCRIPTION Clock accuracy. Value indicating the clock accuracy:
27 to 24
SPDO_BIT[27:24]
Sample frequency. Value indicating the sampling frequency: 0000 = 44.1 kHz 0001 = 48 kHz 0010 = 32 kHz other states = reserved
23 to 20 19 to 16 15 to 8 7 to 6
SPDO_BIT[23:20] SPDO_BIT[19:16] SPDO_BIT[15:8] SPDO_BIT[7:6]
Channel number. Value indicating the channel number (see Table 74). Source number. Value indicating the source number (see Table 75). General information. Value indicating general information (see Table 76). Mode. Value indicating mode 0: 00 = mode 0 other states = reserved
5 to 3
SPDO_BIT[5:3]
Audio sampling. Value indicating the type of audio sampling (linear PCM). For bit SPDO_BIT1 = 0: 000 = two audio samples without pre-emphasis 001 = two audio samples with 50/15 s pre-emphasis 010 = reserved (two audio samples with pre-emphasis) 011 = reserved (two audio samples with pre-emphasis) other states = reserved
2
SPDO_BIT2
Software copyright. Value indicating software for which copyright is asserted or not. If this bit is logic 0, then copyright is asserted; if this bit is logic 1, then no copyright is asserted. Audio sample word. Value indicating the type of audio sample word. If this bit is logic 0, then the audio sample word represents linear PCM samples; if this bit is logic 1, then the audio sample word is used for other purposes. Channel status. Value indicating the consumer use of the status block. This bit is logic 0.
1
SPDO_BIT1
0
SPDO_BIT0
Table 73 Word length SPDO_BIT32 0 0 0 0 0 0 0 0 2003 Apr 10 SPDO_BIT35 0 0 0 0 1 1 1 1 SPDO_BIT34 0 0 1 1 0 0 1 1 58 SPDO_BIT33 0 1 0 1 0 1 0 1 16 bits 18 bits reserved 19 bits 20 bits 17 bits reserved WORD LENGTH not indicated
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
SPDO_BIT32 1 1 1 1 1 1 1 1
SPDO_BIT35 0 0 0 0 1 1 1 1
SPDO_BIT34 0 0 1 1 0 0 1 1
SPDO_BIT33 0 1 0 1 0 1 0 1 20 bits 22 bits
WORD LENGTH indicated
reserved 23 bits 24 bits 21 bits reserved
Table 74 Channel number SPDO_BIT23 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 75 Source number SPDO_BIT19 0 0 0 0 0 0 0 0 1 1 1 2003 Apr 10 SPDO_BIT18 0 0 0 0 1 1 1 1 0 0 0 SPDO_BIT17 0 0 1 1 0 0 1 1 0 0 1 59 SPDO_BIT16 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 SOURCE NUMBER don't care SPDO_BIT22 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPDO_BIT21 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPDO_BIT20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CHANNEL NUMBER don't care A (left for stereo transmission) B (right for stereo transmission) C D E F G H I J K L M N O
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
SPDO_BIT19 1 1 1 1 1
SPDO_BIT18 0 1 1 1 1
SPDO_BIT17 1 0 0 1 1
SPDO_BIT16 1 0 1 0 1 11 12 13 14 15
SOURCE NUMBER
Table 76 General information SPDO_BIT[15:8] 00000 000 Lxxxx 001 Lxxxx 010 Lxxxx 011 Lxxxx 100 Lxxxx 110 Lxxxx 101 Lxx00 110 Lxx10 110 Lxxx1 000 L1000 000 Lxxxx 111 Lxxx0 000 12.3 12.3.1 Read registers mapping INTERPOLATOR general laser optical products digital-to-digital converters and signal processing products magnetic tape or disc based products broadcast reception of digitally encoded audio signals with video signals broadcast reception of digitally encoded audio signals without video signals musical instruments, microphones and other sources without copyright information analog-to-digital converters for analog signals without copyright information analog-to-digital converters for analog signals which include copyright information in the form of Cp- and L-bit status solid state memory based products experimental products not for commercial sale reserved reserved, except 000 0000 and 000 0001L FUNCTION
Table 77 Register address 18H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 13 - 5 12 - 4 11 - 3 10 - 2 9 - 1 8 - 0
SDETR2 SDETL2 SDETR1 SDETL1 MUTE_STATE_M MUTE_STATE_CH2 MUTE_STATE_CH1
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 78 Description of register bits (address 18H) BIT 15 to 7 6 - SDETR2 SYMBOL reserved DESCRIPTION
UDA1355H
Silence detector channel 2 right. If this bit is logic 0 then there is no silence detection for the right input of channel 2; if this bit is logic 1 then there is silence detection for the right input of channel 2. Silence detector channel 2 left. If this bit is logic 0 then there is no silence detection for the left input of channel 2; if this bit is logic 1 then there is silence detection for the left input of channel 2. Silence detector channel 1 right. If this bit is logic 0 then there is no silence detection for the right input of channel 1; if this bit is logic 1 then there is silence detection for the right input of channel 1. Silence detector channel 1 left. If this bit is logic 0 then there is no silence detection for the left input of channel 1; if this bit is logic 1 then there is silence detection for the left input of channel 1. Mute status interpolator. If this bit is logic 0 then the interpolator is not muted; if this bit is logic 1 then the interpolator is muted. Mute status channel 2. If this bit is logic 0 then the interpolator channel 2 is not muted; if this bit is logic 1 then the interpolator channel 2 is muted. Mute status channel 1. If this bit is logic 0 then the interpolator channel 1 is not muted; if this bit is logic 1 then the interpolator channel 1 is muted.
5
SDETL2
4
SDETR1
3
SDETL1
2 1 0
MUTE_STATE_M MUTE_STATE_CH2 MUTE_STATE_CH1
12.3.2
DECIMATOR
Table 79 Register address 28H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 MT_ADC_stat 9 - 1 - 8 - 0 OVERFLOW
Table 80 Description of register bits (address 28H) BIT 15 to 3 2 1 0 - MT_ADC_stat - OVERFLOW SYMBOL reserved Mute status decimator. If this bit is logic 0 then the decimator is not muted; if this bit is logic 1 then the decimator is muted. reserved Overflow decimator. If this bit is logic 0 then there is no overflow in the decimator (digital level above -1.16 dB.); if this bit is logic 1 then there is an overflow in the decimator. DESCRIPTION
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Stereo audio codec with SPDIF interface
12.3.3 SPDIF INPUT
UDA1355H
Table 81 Register address 59H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 - 9 - 1 B_ERR 8 SPDO_STATUS 0 SPDIF_LOCK
Table 82 Description of register bits (address 59H) BIT 15 to 9 8 7 to 2 1 0 - SPDO_STATUS - B_ERR SPDIF_LOCK SYMBOL reserved SPDIF encoder output status. If this bit is logic 0 then the SPDIF encoder output is enabled; if this bit is logic 1 then the SPDIF encoder output is disabled. reserved Bit error detection. If this bit is logic 0 then there is no biphase error; if this bit is logic 1 then there is a biphase error. SPDIF lock indicator. If this bit is logic 0 then the SPDIF decoder block is not in lock; if this bit is logic 1 then the SPDIF decoder block is in lock. DESCRIPTION
Table 83 Register address 5CH (left) and 5FH (right); note 1 BIT Symbol BIT Symbol Note 1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72. Table 84 register addresses 5BH (left) and 5EH (right); note 1 BIT Symbol 15 SPDI_ BIT31 7 SPDI_ BIT23 14 SPDI_ BIT30 6 SPDI_ BIT22 13 SPDI_ BIT29 5 SPDI_ BIT21 12 SPDI_ BIT28 4 SPDI_ BIT20 11 SPDI_ BIT27 3 SPDI_ BIT19 10 SPDI_ BIT26 2 SPDI_ BIT18 9 SPDI_ BIT25 1 SPDI_ BIT17 8 SPDI_ BIT24 0 SPDI_ BIT16 15 - 7 SPDI_ BIT39 14 - 6 SPDI_ BIT38 13 - 5 SPDI_ BIT37 12 - 4 SPDI_ BIT36 11 - 3 SPDI_ BIT35 10 - 2 SPDI_ BIT34 9 - 1 SPDI_ BIT33 8 - 0 SPDI_ BIT32
BIT Symbol Note
1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72.
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Preliminary specification
Stereo audio codec with SPDIF interface
Table 85 register address 5AH (left) and 5DH (right); see note 1 BIT Symbol 15 SPDI_ BIT15 7 SPDI_ BIT7 14 SPDI_ BIT14 6 SPDI_ BIT6 13 SPDI_ BIT13 5 SPDI_ BIT5 12 SPDI_ BIT12 4 SPDI_ BIT4 11 SPDI_ BIT11 3 SPDI_ BIT3 10 SPDI_ BIT10 2 SPDI_ BIT2
UDA1355H
9 SPDI_ BIT9 1 SPDI_ BIT1
8 SPDI_ BIT8 0 SPDI_ BIT0
BIT Symbol Note
1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72. 13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all voltage referenced to ground. SYMBOL VDD Tstg Tamb Vesd Ilu(prot) Isc(DAC) PARAMETER supply voltage storage temperature ambient temperature electrostatic discharge voltage latch-up protection current short-circuit current of DAC Machine Model (MM); note 3 Tamb = 125 C; VDD = 3.6 V Tamb = 0 C;VDD = 3 V; note 4 output short-circuit to VSSA1 output short-circuit to VDDA1 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant. 4. DAC operation after short-circuiting cannot be guaranteed. 14 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 70 UNIT K/W - - 20 100 mA mA note 1 CONDITIONS MIN. 2.7 -65 -40 Human Body Model (HBM); note 2 -3000 -250 - MAX. 5.0 +125 +85 +3000 +250 100 UNIT V C C V V mA
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Stereo audio codec with SPDIF interface
UDA1355H
15 CHARACTERISTICS VDD = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified; note 1. SYMBOL Supplies VDDA1 VDDA2 VDDX VDDI VDDE IDDA1 DAC supply voltage ADC supply voltage crystal oscillator and PLL supply voltage digital core supply voltage digital pad supply voltage DAC supply current fs = 48 kHz; power-on fs = 96 kHz; power-on fs = 48 kHz; power-down fs = 96 kHz; power-down IDDA2 ADC supply current fs = 48 kHz; power-on fs = 96 kHz; power-on fs = 48 kHz; power-down fs = 96 kHz; power-down IDDX IDDI IDDE crystal oscillator and PLL supply current digital core supply current digital pad supply current fs = 48 kHz; power-on fs = 96 kHz; power-on fs = 48 kHz; all on fs = 96 kHz; all on fs = 48 kHz; all on fs = 96 kHz; all on Digital input pins VIH VIL Vhys(RESET) |ILI| Ci VOH VOL IL(max) Rpu Rpd VIH VIM VIL HIGH-level input voltage LOW-level input voltage hysteresis on pin RESET input leakage current input capacitance IOH = -2 mA IOL = 2 mA 0.8VDD -0.5 - - - 0.85VDD - - 16 16 - - 0.8 - - - - 3 33 33 - - - VDD + 0.5 +0.2VDD - 2 10 - 0.4 - 78 78 V V V A pF 2.7 2.7 2.7 2.7 2.7 - - - - - - - - - - - - - - 3.0 3.0 3.0 3.0 3.0 4.7 4.7 1.7 1.7 10.2 10.4 0.2 0.2 0.9 1.2 18.2 34.7 0.5 0.7 3.6 3.6 3.6 3.6 3.6 - - - - - - - - - - - - - - V V V V V mA mA A A mA mA A A mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital output pins HIGH-level output voltage LOW-level output voltage maximum output load (nominal) pull-up resistance pull-down resistance V V mA k k
3-level input pins HIGH-level input voltage MID-level input voltage LOW-level input voltage 0.9VDD 0.4VDD 0 VDD 0.6VDD 0.5 V V V
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Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL Reference voltage VREF
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
reference voltage on pin REF
with respect to VSSA
0.45VDD
0.5VDD 0.55VDD
V
Digital-to-analog converter Vo(rms) Vo (THD+N)/S output voltage (RMS value) output voltage unbalance total harmonic distortion-plus-noise to signal ratio IEC 60958 input; fs = 48 kHz at 0 dB at -20 dB at -60 dB; A-weighted IEC 60958 input; fs = 96 kHz at 0 dB at -60 dB; A-weighted S/N signal-to-noise ratio IEC 60958 input; code = 0; A-weighted fs = 48 kHz fs = 96 kHz cs RL CL Ro Io(max) channel separation load resistance load capacitance output resistance maximum output current (THD + N)/S < 0.1%; RL = 5 k note 2 fi = 1 kHz tone - - - 3 - - - 98 96 100 - - 0.13 tbf - - - - 200 3.0 - dB dB dB k pF mA - - -83 -37 - - dB dB - - - -88 -75 -37 - - - dB dB dB - - 900 0.1 - - mV dB
Analog-to-digital converter VADCP VADCN Vi(rms) Vi (THD+N)/S positive ADC reference voltage negative ADC reference voltage input voltage (RMS value) input voltage unbalance total harmonic distortion-plus-noise to signal ratio fs = 48 kHz at 0 dB at -60 dB; A-weighted fs = 96 kHz at 0 dB at -60 dB; A-weighted S/N signal-to-noise ratio code = 0; A-weighted fs = 48 kHz fs = 96 kHz cs channel separation - - - 97 95 100 - - - dB dB dB - - -85 -35 - - dB dB - - -85 -35 - - dB dB Vo = -1.16 dBFS digital output - - - - VDDA2 0.0 1.0 0.1 - - - - V V V dB
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Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL IEC 60958 inputs Vi(p-p) Ri Vhys IDD(diff) Ptot
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
input voltage (peak-to-peak value) input resistance hysteresis voltage IDD(DAC,input)/IDD(DAC,no input) total power consumption IEC 60958 input; fs = 48 kHz DAC in playback mode
0.2 - - -
0.5 6 40 tbf
3.3 - - -
V k mV -
Power consumption - 74 63 - - mW mW
DAC in Power-down mode - Notes
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 must be used in order to prevent oscillations in the output. 16 TIMING CHARACTERISTICS VDD = 2.7 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k; unless otherwise specified. SYMBOL Device reset trst PLL lock time tlock time-to-lock fs = 32 kHz fs = 44.1 kHz fs = 48 kHz fs = 96 kHz I2S-bus interface (see Fig.20) Tcy(BCK) tBCKH tBCKL tr tf tsu(DATAI) th(DATAI) td(DATAO-BCK) td(DATAO-WS) th(DATAO) tsu(WS) th(WS) 2003 Apr 10 bit clock period bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time data output to bit clock delay data output to word select delay data output hold time word select set-up time word select hold time 66
1/ 128fs
PARAMETER
CONDITIONS - - - - -
MIN.
TYP.
MAX. - - - - - - - - 20 20 - - 30 30 - - -
UNIT s ms ms ms ms
reset time
250
85.0 63.0 60.0 40.0 - - - - - - - - - - - -
ms ns ns ns ns ns ns ns ns ns ns ns
30 30 - - 10 10 - - 0 10 10
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL
PARAMETER
CONDITIONS - - 500 250 250 190 190 190 190 190 190
MIN.
TYP. - - - - - - - - - - -
MAX.
UNIT
L3-bus interface (see Figs 21 and 22) tr tf Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tstp(L3) tsu(L3)DA rise time fall time L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA delay time in data transfer mode L3DATA disable time for read data note 1 note 1 note 2 note 2 note 2 10 10 - - - - - - - - - ns/V ns/V ns ns ns ns ns ns ns ns ns
th(L3)DA
30
-
-
ns
td(L3)R tdis(L3)R
0 0
- -
50 50
ns ns
I2C-bus interface (see Fig.23) fSCL tLOW tHIGH tr tf tHD;STA tSU;STA tSU;STO tBUF tSU;DAT SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL note 3 fall time SDA and SCL hold time START condition set-up time repeated START set-up time STOP condition bus free time data set-up time note 3 note 4 0 1.3 0.6 20 + 0.1Cb 20 + 0.1Cb 0.6 0.6 0.6 between a STOP and START 1.3 condition 100 - - - - - - - - - - 400 - - 300 300 - - - - - kHz s s ns ns s s s s ns
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Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL tHD;DAT tSP CL Notes
PARAMETER data hold time pulse width of spikes load capacitance note 5
CONDITIONS 0 0 - for each bus line
MIN.
TYP. - - -
MAX. - 50 400
UNIT s ns pF
1. In order to prevent digital noise interfering with the L3-bus communication, the rise and fall times should be as small as possible. 2. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 164fs cycle. 3. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. 4. After this period, the first clock pulse is generated. 5. To be suppressed by the input filter.
handbook, full pagewidth
WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK)
tr
tf
t d(DATAO-WS)
t h(DATAO)
t su(DATAI) t h(DATAI) DATAI
MGS756
Fig.20 I2S-bus interface timing.
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Stereo audio codec with SPDIF interface
UDA1355H
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.21 L3-bus interface timing for address mode.
handbook, full pagewidth
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
th(L3)DA L3DATA write
tsu(L3)DA
BIT 0
BIT 7
L3DATA read td(L3)R tdis(L3)R
MBL566
Fig.22 L3-bus interface timing for data transfer mode (write and read).
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SDA t BUF t LOW tr tf t HD;STA t SP
Philips Semiconductors
Stereo audio codec with SPDIF interface Stereo audio codec with SPDIF interface
Fig.23 I2C-bus interface timing.
handbook, full pagewidth
70 70
SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr
MBC611
P
Preliminary specification
UDA1355H UDA1355H
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
UDA1355H
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-01 03-02-25
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Stereo audio codec with SPDIF interface
18 SOLDERING 18.1 Introduction to soldering surface mount packages
UDA1355H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferably be kept: * below 220 C for all the BGA packages and packages with a thickness 2.5mm and packages with a thickness <2.5 mm and a volume 350 mm3 so called thick/large packages * below 235 C for packages with a thickness <2.5 mm and a volume <350 mm3 so called small/thin packages. 18.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
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Stereo audio codec with SPDIF interface
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes not suitable not suitable(3)
UDA1355H
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Stereo audio codec with SPDIF interface
19 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
UDA1355H
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 20 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Stereo audio codec with SPDIF interface
22 PURCHASE OF PHILIPS I2C COMPONENTS
UDA1355H
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp76
Date of release: 2003
Apr 10
Document order number:
9397 750 09925

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